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e preliminary information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of intel products. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. the intel 430tx pciset may contain design defects or errors known as errata. current characterized errata are available on request. third-party brands and names are the property of their respective owners. ? intel corporation 1997 february 1997 order number: 290559-001 supports mobile and desktop supports the pentium ? processor family host bus at 66 mhz and 60 mhz at 3.3v and 2.5v pci 2.1 compliant integrated data path integrated dram controller ? ? 4 mbytes to 256 mbytes main memory ? ? 64-mbit dram/sdram technology support ? ? fpm (fast page mode), edo and sdram dram support ? ? 6 ras lines available ? ? integrated programmable strength for dram interface ? ? cas-before-ras refresh, extended refresh and self refresh for edo ? ? cas-before-ras and self refresh for sdram integrated l2 cache c ontroller ? ? 64-mb dram cacheability ? ? direct mapped organization ? write back only ? ? supports 256k and 512k pipelined burst sram and dram cache sram ? ? cache hit read/write cycle timings at 3-1-1-1 ? ? back-to-back read/write cycles at 3-1-1-1-1-1-1-1 ? ? 64k x 32 sram also supported fully synchronous, minimum latency 30/33-mhz pci bus interface ? ? five pci bus masters (including piix4) ? ? 10 dword pci-to-dram read prefetch buffer ? ? 18 dword pci-dram post buffer ? ? multi-transaction timer to support multiple short pci transactions power management features ? ? pci clkrun# support ? ? dynamic stop clock support ? ? suspend to ram (str) ? ? suspend to disk (std) ? ? power on suspend (pos) ? ? internal clock control ? ? sdram and edo self refresh during suspend ? ? acpi support ? ? compatible smram (c_smram) and extended smram (e_smram) ? ? smm writeback cacheable in e_smram mode up to 1 mb ? ? 3.3/5v dram, 3.3/5v pci 3.3/5v tag and 3.3/2.5 sram support test features ? ? nand tree support for all pins supports the universal serial bus (usb) 324-pin mbga 430tx pciset xcelerated controller (mtxc) with integrated data paths the intel 430tx pciset (430tx) consists of the 82439TX system controller (mtxc) and the 82371ab pci isa ide xcelerator (piix4). the 430tx supports both mobile and desktop architectures. the 430tx forms a host-to- pci bridge and provides the second level cache control and a full function 64-bit data path to main memory. the mtxc integrates the cache and main memory dram control functions and provides bus control to transfers between the cpu, cache, main memory, and the pci bus. the second level (l2) cache controller supports a writeback cache policy for cache sizes of 256 kbytes and 512 kbytes. cacheless designs are also supported. the cache memory can be implemented with pipelined burst srams or dram cache srams. an external tag ram is used for the address tag and an internal tag ram for the cache line status bits. for the mtxc dram controller, six rows are supported for up to 256 mbytes of main memory. the mtxc is highly integrated by including the data path into the same bga chip. using the snoop ahead feature, the mtxc allows pci masters to achieve full pci bandwidth. for increased system performance, the mtxc integrates posted write and read prefetch buffers. the 430tx integrates many power management features that enable the system to save power when the system resources become idle. intel 430tx pciset: 82439TX system controller (mtxc)
82439TX (mtxc) e 2 preliminary a[31:0] devsel# par req[3:0]# phld# plock# irdy# trdy# frame# c/be[3:0]# cas[7:0]#/dqm[7:0]# scas[a,b]# mweb# cke/maa0, ckeb/maa1 cache# brdy# w/r# hitm# boff# na# ken#/inv be[7:0]# m/io# d/c# coe# cadv# cache interface hd[63:0] ad[31:0] ccs# hclkin hlock# smiact# tio[7:0] krqak/cs4_64# bwe# ras[5:0]#/cs[5:0]# sras[a,b]# md[63:0] clocks, reset, test, and power mgnt pclkin test# susclk susstat1# clkrun# dram interface pci interface host interface ads# eads# ahold twe# gwe# cads# rst# mwe# ma[11:0] phlda# gnt[3:0]# stop# mtx_blk mtxc simplified block diagram
e 82439TX (mtxc) 3 preliminary contents page 1.0. architecture overview ................................ ................................ ................................ ........................ 6 2.0. signal description ................................ ................................ ................................ ................................ .. 8 2.1. mtxc signals ................................ ................................ ................................ ................................ ............... 8 2.1.1. host interface ................................ ................................ ................................ ................................ ......... 8 2.1.2. dram interface ................................ ................................ ................................ ................................ ... 10 2.1.3. secondary cache interface ................................ ................................ ................................ ................. 1 2 2.1.4. pci interface ................................ ................................ ................................ ................................ ........ 13 2.1.5. test and clock ................................ ................................ ................................ ................................ ..... 14 2.1.6. power management ................................ ................................ ................................ ............................. 14 2.1.7. power and ground pins ................................ ................................ ................................ ....................... 14 2.2. mtxc strapping options ................................ ................................ ................................ ............................ 15 2.3. power planes ................................ ................................ ................................ ................................ .............. 15 2.4. power sequencing requirements ................................ ................................ ................................ .............. 16 2.5. signal states during and after a hard reset ................................ ................................ ............................. 17 3.0. register description ................................ ................................ ................................ ........................... 18 3.1. i/o mapped registers ................................ ................................ ................................ ................................ . 18 3.1.1. pm2_cntrl ? pm2 register block ................................ ................................ ................................ .... 19 3.1.2. confadd ? configuration address register ................................ ................................ ..................... 19 3.1.3. confdata ? configuration data register ................................ ................................ ......................... 20 pci configuration space mapped registers ................................ ................................ ................................ ..... 20 3.1.4. vid ? vendor identification register ................................ ................................ ................................ .... 23 3.1.5. did ? device identification register ................................ ................................ ................................ .... 23 3.1.6. pcicmd ? pci command register ................................ ................................ ................................ ..... 23 3.1.7. pcists ? pci status register ................................ ................................ ................................ ............ 24 3.1.8. rid ? revision identification register ................................ ................................ ................................ .. 25 3.1.9. classc ? class code register ................................ ................................ ................................ .......... 25 3.1.10. mlt ? master latency timer register ................................ ................................ ............................... 25 3.1.11. hedt ? header type register ................................ ................................ ................................ .......... 26 3.1.12. bist ? bist register ................................ ................................ ................................ ......................... 26 3.1.13. acon ? arbitration control register ................................ ................................ ................................ . 26 3.1.14. pcon ? pci control register ................................ ................................ ................................ ............ 27 3.1.15. cc ? cache control register ................................ ................................ ................................ ............. 27 3.1.16. cec ? extended cache control register ................................ ................................ .......................... 29 3.1.17. sdramc ? sdram control register ................................ ................................ ............................... 29 3.1.18. dramec ? dram extended control register ................................ ................................ ................. 31 3.1.19. dramc ? dram control register ................................ ................................ ................................ .... 32 3.1.20. dramt ? dram timing register ................................ ................................ ................................ ...... 33
82439TX (mtxc) e 4 preliminary 3.1.21. pam ? programmable attribute map registers (pam[6:0]) ................................ ............................... 34 3.1.22. drb ? dram row boundary registers ................................ ................................ ............................ 38 3.1.23. drth ? dram row type register high ................................ ................................ .......................... 40 3.1.24. drtl ? dram row type register low ................................ ................................ ............................ 41 3.1.25. mtt ? multi-transaction timer register (reserved test mode register) ................................ ........ 41 3.1.26. esmramc ? extended system management ram control register ................................ .............. 42 3.1.27. smramc ? system management ram control register ................................ ................................ 43 3.1.28. mctl ? miscellaneous control register ................................ ................................ ............................ 45 4.0. functional description ................................ ................................ ................................ ...................... 46 4.1. host interface ................................ ................................ ................................ ................................ .............. 46 4.2. secondary cache interface ................................ ................................ ................................ ........................ 46 4.2.1. clock latencies ................................ ................................ ................................ ................................ .... 49 4.2.2. snoop cycles ................................ ................................ ................................ ................................ ....... 49 4.2.3. dram cache second level cache mode ................................ ................................ .......................... 50 4.3. dram interface ................................ ................................ ................................ ................................ .......... 50 4.3.1. dram organization ................................ ................................ ................................ ............................. 51 4.3.2. configuration requirements ................................ ................................ ................................ ................ 53 4.3.3. dram address translation ................................ ................................ ................................ ................. 57 4.3.4. dram paging ................................ ................................ ................................ ................................ ...... 57 4.3.5. dram types ................................ ................................ ................................ ................................ ........ 57 4.3.5.1. fpm mode ................................ ................................ ................................ ................................ ..... 57 4.3.5.2. edo mode ................................ ................................ ................................ ................................ .... 57 4.3.5.3. sdram mode ................................ ................................ ................................ ............................... 57 4.3.6. auto detection ................................ ................................ ................................ ................................ ...... 59 4.3.7. dram performance ................................ ................................ ................................ ............................. 59 4.3.8. dram refresh ................................ ................................ ................................ ................................ ..... 62 4.4. pci clk control (clkrun#) ................................ ................................ ................................ ..................... 62 4.4.1. clocking states ................................ ................................ ................................ ................................ .... 62 4.4.2. operation ................................ ................................ ................................ ................................ ............. 62 4.5. smram memory space ................................ ................................ ................................ ............................. 62 4.5.1. compatible smram (c_smram) ................................ ................................ ................................ ....... 62 4.5.2. extended smram (e_smram) ................................ ................................ ................................ .......... 62 4.5.3. smram programming considerations ................................ ................................ ................................ 64 4.6. low power states ................................ ................................ ................................ ................................ ....... 64 4.6.1. chip standby ................................ ................................ ................................ ................................ ........ 65 4.6.2. suspend/resume ................................ ................................ ................................ ................................ 65 4.6.2.1. power transition changes ................................ ................................ ................................ ............ 66 4.7. pci interface ................................ ................................ ................................ ................................ ............... 67 4.8. system arbitration ................................ ................................ ................................ ................................ ....... 68 4.8.1. priority scheme and bus grant ................................ ................................ ................................ ........... 68 4.8.2. cpu policies ................................ ................................ ................................ ................................ ........ 70
e 82439TX (mtxc) 5 preliminary 5.0. clocks and reset ................................ ................................ ................................ ................................ .. 70 5.1. clock generation and distribution ................................ ................................ ................................ ............... 70 5.2. reset sequencing ................................ ................................ ................................ ................................ .... 70 6.0. pinout information ................................ ................................ ................................ ............................... 71 7.0. mtxc package information ................................ ................................ ................................ ................ 76 8.0. testability ................................ ................................ ................................ ................................ ................. 79 8.1. nand tree mode ................................ ................................ ................................ ................................ ....... 79 8.2. nand chain mode ................................ ................................ ................................ ................................ ..... 79
82439TX (mtxc) e 6 preliminary 1. 0. architecture overview the mtxc host bridge provides a completely integrated solution for the system controller and datapath components in a pentium processor system. the mtxc supports all pentium family processors since p54c, it has 64-bit host and dram bus interface, 32-bit pci bus interface, second level cache interface, and it integrates the pci arbiter. the mtxc interfaces with the pentium processor host bus, a dedicated memory data bus, and the pci bus (see figure 1). the mtxc bus interfaces are designed to interface with 2.5v, 3.3v and 5v busses. the mtxc implements 2.5v and 3.3v drivers and 5v tolerant receivers. the mtxc connects directly to the pentium processor 3.3v or 2.5v host bus, directly to 5v or 3.3v drams, and directly to the 5v or 3.3v pci bus. the 430tx also interfaces directly to the 3.3v or 5.0v tagram and 3.3v cache. the mtxc works with the pci ide/isa accelerator 4 (piix4). the piix4 provides the pci-to-isa/eio bridge functions along with other features such as a fast ide interface (pio mode 4 and ultra dma/33), plug-n-play port, apic interface, pci 2.1 compliance, smbus interface, and universal serial bus host controller functions. dram interface the dram interface is a 64-bit data path that supports standard (or fast) page mode (fpm), extended data out (edo) and synchronous dram (sdram) memory. the dram controller inside the mtxc is capable of generating 3-1-1-1 for posted writes for any type of dram that is used. while read performance is 6-1-1-1 for sdram, 5-2-2-2 for edo, and 6-3-3-3 for fpm. the dram interface supports 4 mbytes to 256 mbytes with six ras lines. the mtxc supports 4-mbit, 16-mbit, and 64-mbit dram and sdram technology, both symmetrical and asymmetrical. parity is not supported, and for loading reasons, x32 and x64 simms/dimms/so-dimms should be used. second level cache the second level cache is direct mapped and supports both 256-kbyte and 512-kbyte sram configuration using pipeline burst sram or dram cache sram. the cache performance is 3-1-1-1 for line read/write and 3-1-1-1-1-1-1-1 for back to back reads that are pipelined. cacheless configuration is also supported. pci interface the pci interface is 2.1 compliant and supports up to four pci bus masters in addition to the piix4 bus master requests. datapath and buffers the mtxc contains three sets of data buffers for optimizing data flow. a five qword deep dram write buffer is provided for cpu-to-dram writes, second level cache write backs, and pci-to-dram transfers. this buffer is used to achieve 3-1-1-1 posted writes to dram and also provides dword merging and burst merging for cpu- to-dram write cycles. in addition, an extra line of buffering is provided that is combined with the dram write buffer to supply an 18 dword deep buffer for pci to main memory writes. a five dword buffer is provided for cpu-to-pci writes to help maximize the bandwidth for graphic writes to the pci bus. also, five qwords of prefetch buffering has been added to the pci-to-dram read path that allows up to two lines of data to be prefetched at an x-2-2-2 rate. the mtxc interfaces directly to the host and dram data bus. power management features the mtxc implements extensive power management features. the clkrun# feature enables controlling of the pci clock (on/off). the mtxc supports pos, str, std, and soft-off suspend states. susclk and
e 82439TX (mtxc) 7 preliminary susstat1# signals are used for implementing suspend logic. the mtxc supports two smram modes; compatible smram (c_smram) and extended smram (e_smram). the c_smram is the traditional smram feature implemented in intel pcisets. the e_smram is a new feature that supports writeback cacheable smram space up to 1 mbytes. in order to minimize the idle power, the internal clock in mtxc is turned off (gated off) when there is no activity on the host and pci bus. pci bus (3.3v or 5v, 30/33 mhz) dram interface (3.3v or 5v) main memory (dram) pentium ? processor host bus (3.3v or 2.5v i/o; 60-66 mhz) second level cache cache (pbsram) tag cntl tag cntl tio[7:0] 82349tx (mtxc) bmi ide ultra dma/33 cd rom hard disk isa/eio bus (3.3v; 5v tolerant) usb 1 usb 2 universal serial bus 82371ab (piix4) gp[i,o] (30+) smb (i 2 c) audio kbd sp, pp, fdc, ir bios pci docking connector 82380fb (mpci2) pci bus (5v) 82380ab (misa) isa bus (5v) isa slots pci slots for mobile docking stations only pci slots hard disk mtx_sys figure 1 . mtxc system block diagram
82439TX (mtxc) e 8 preliminary 2. 0. signal description this section provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the ? # ? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ? # ? is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used exclusively. this is done to avoid confusion when working with a mixture of ? active low ? and ? active high ? signal. the term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate, or negation indicates that a signal is inactive. the i/o buffer types are shown below: buffer type description i input only signal o totem pole output i/o bi-direction, tri-state input/output pin s/t/s sustained tri-state od open drain 3.3v/2.5v indicates the buffer is 3.3v or 2.5v only, depending on the voltage (3.3v or 2.5v) connected to vccx pins. 3.3v/5v indicates that the output is 3.3v and input is 3.3v receiver with 5v tolerance. 5v indicates 3.3v receiver with 5v tolerance. 2.1. mtxc signals 2.1.1. host interface name type description a[31:3] i/o 3.3v/2.5v address bus. a[31:3] connects to the address bus of the cpu. during cpu cycles a[31:3] are inputs. the mtxc drives a[31:3] during inquire cycles on behalf of pci initiators. bits a[31:26] act as inputs when rst# is active be[7:0]# i 3.3v/2.5v byte enables. the cpu byte enables indicate which byte lane the current cpu cycle is accessing. all eight byte lanes must be provided to the cpu if the cycle is a cacheable read regardless of the state of be[7:0]#. ads# i 3.3v/2.5v address status. cpu asserts ads# in t1 of the cpu bus cycle. brdy# o 3.3v/2.5v bus ready. the mtxc asserts brdy# to indicate to the cpu that data is available on reads or has been received on writes. na# o 3.3v/2.5v next address. this signal is asserted by the mtxc to indicate to the processor that it is ready to process a second cycle.
e 82439TX (mtxc) 9 preliminary name type description ahold o 3.3v/2.5v address hold. the mtxc asserts ahold when a pci initiator is performing a cycle to dram. ahold is held for the duration of the pci burst transfer. the mtxc will negate ahold when the completion of the pci to dram read or write cycles complete and during pci peer transfers. ahold is kept asserted while phlda# is asserted (i.e., duration of piix4 granting). eads# o 3.3v/2.5v external address strobe. asserted by the mtxc to inquire the first level cache when servicing pci master references of dram. boff# o 3.3v/2.5v back off. asserted by the mtxc when required to terminate a cpu cycle that was in progress. hitm# i 3.3v/2.5v hit modified. asserted by the cpu to indicate that the address presented with the last assertion of eads# is modified in the first level cache and needs to be written back. m/io#, d/c#, w/r# i 3.3v/2.5v memory/io; data/control; write/read. asserted by the cpu with ads# to indicate the type of cycle that the system needs to perform. hlock# i 3.3v/2.5v host lock. all cpu cycles sampled with the assertion of hlock# and ads#, until the negation of hlock# must be atomic, i.e. no pci activity to dram is allowed. cache# i 3.3v/2.5v cache. asserted by the cpu during a read cycle to indicate the cpu will perform a burst line fill. asserted by the cpu during a write cycle to indicate the cpu will perform a burst writeback cycle. if cache# is asserted to indicate cacheability, the mtxc will assert ken# either with the first brdy#, or with na# if na# is asserted before the first brdy#. ken#/inv o 3.3v/2.5v ken/invalidate. ken#/inv functions as both the ken# signal during cpu read cycles, and the inv signal during l1 snoop cycles. during cpu cycles, ken#/inv is normally low. ken#/inv is driven high during the 1st brdy# or na# assertion of a non-l1-cacheable cpu read cycle. ken#/inv is driven high(low) during the eads# assertion of a pci master dram write(read) snoop cycle. note that ken#/inv operation during snoop cycles is independent of the flce bit programming. smiact# i 3.3v/2.5v system management interrupt active. this is asserted by the cpu when it is in system management mode as a result of an smi. this signal must be sampled active with ads# for the processor to access the smm space of dram, located at a0000h, after smm space has been loaded and locked by bios at system boot. hd[63:0] i/o 3.3v/2.5v host data. these signals are connected to the cpu data bus. these signals have internal pull-down resistors. notes: all of the signals in the host interface are described in the pentium processor data sheet. the preceding table highlights mtxc specific uses of these signals.
82439TX (mtxc) e 10 preliminary 2.1.2. dram interface name type description ras[3:0]# or cs[3:0]#, ras4#/cs4#/ ba1, ras5#/cs5#/ ma13 o 3.3 v row address strobe ? rasx# (edo/fpm). these pins select the dram row. chip select ? csx# (sdram). these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. note: for 64mbit sdram support, ba1/ma12 and ma13 are muxed with the ras4# and ras5# signals, respectively. when sdramc[bit 1]=1, ba1 and ma13 are driven out on these lines. cas[7:0]# or dqm[7:0] o 3.3 v column address strobe (edo/fpm). these pins select the dram column. input/output data mask sdram). these pins act as synchronized output enables during a read cycle and a byte mask during a write cycle. the read cycles require tdqz clock latency before the functions are actually performed. in case of a write cycle, word mask functions are performed in the same cycle (0 cycle latency). ma[11:0] o 3.3 v memory address (edo/fpm/sdram). this is the row and column address for dram. these buffers now include programmable size selection, as controlled by the dramec[mad] bit. for 64-mbit sdram support ba1/ma12 and ma13 are muxed with the ras4# and ras5# signals, respectively. mweb# o 3.3 v memory write enable (second copy) (edo/fpm/sdram). mwe# should be used as the write enable for the memory data bus. this signal has programmable buffer size selection. mwe# o 3.3 v memory write enable (edo/fpm/sdram). mwe# should be used as the write enable for the memory data bus. this signal has programmable buffer size selection. sras[a,b]# o 3.3 v sdram row address strobe (sdram). when asserted, this signal latches row address on the positive edge of the clock. this signal also allows row access and precharge. two copies are provided for loading purpose. these signals have programmable buffer size selection. scas[a,b]# o 3.3 v sdram column address strobe (sdram). when asserted, this signal latches column address on the positive edge of the clock. this signal also allows column access. two copies provided for loading purpose. these signals have programmable buffer size selection. cke/maa0 o 3.3 v sdram clock enable (sdram). sdram clock enable pin. when this signal is negated, sdram enters power down mode. this signal is also muxed to provide a second copy of memory address ma0 (maa0). the ma function is selected via drt[bit2] (offset 67h). mtxc negates cke (and ckeb) when susstat1# is asserted. note that mtxc asserts cke (and ckeb) for all rows (i.e., cke and ckeb cannot be selectively asserted for certain rows and negated for other rows).
e 82439TX (mtxc) 11 preliminary name type description ckeb/maa1 o 3.3 v sdram clock enable (sdram) (second copy). sdram clock enable pin. when this signal is negated, sdram enters into power down mode. note that this signal is not implemented in the ? suspend we ll ? and should not be used if suspend to ram (str) is implemented. this signal is also muxed to provide a second copy of memory address ma1 (maa1). the ma function is selected via drt[bit2] (offset 67h). mtxc negates cke (and ckeb) when susstat1# is asserted. note that mtxc asserts cke (and ckeb) for all rows (i.e., cke and ckeb cannot be selectively asserted for certain rows and negated for other rows). md[63:0] i/o 3.3v/5v memory data. these signals are connected to the dram data bus. these signals have internal pull-down resistors
82439TX (mtxc) e 12 preliminary 2.1.3. secondary cache int erface name type description cadv# o 3.3v cache advance. assertion causes the pbsram in the secondary cache to advance to the next qword in the cache line. cads# o 3.3v cache address strobe. assertion causes the pbsram in the secondary cache to load the pbsram address register from the pbsram address pins. ccs# o 3.3v cache chip select (ccs#). the second level cache will power up, if necessary, and perform an access if this signal is asserted when cads# is asserted. the second level cache will power down if this signal is negated when cads# is asserted. when ccs# is negated the second level cache will ignore ads#. if ccs# is asserted when ads# is asserted, the second level cache will power up, if necessary, and perform an access. coe# o 3.3v cache output enable. the secondary cache data rams drive the cpus data bus when coe# is asserted. gwe# o 3.3v global write enable. gwe# assertion causes all the byte lanes to be written into the secondary cache data rams, if they are powered up. bwe# o 3.3v byte write enable. asserted low with gwe#=high to enable using host?s be[7:0]# to be used to control byte lanes to pipeline burst sram cache. tio[7:0] i/o 3.3v/5v tag address. these are inputs during cpu accesses and outputs during second level cache line fills and second level cache line invalidates due to inquire cycles. these signals have internal pull-down resistors. twe# o 3.3v tag write enable. when asserted, new state and tag addresses are written into the external tag. krqak/ cs4_64# i/o 3.3v krqak/chip select 4 (for 64-mb technology). this pin is a dual-function signal. krqak is used in a dram cache l2 implementation and is a bi-directional refresh request/acknowledge. the cs4_64# function is used to generate the fifth chip select line in a sdram l2 cache implementation that supports five rows of 64-mbit sdram. during a hard reset, this signal is sampled to determine if dram cache is in the system (see mtxc strapping options). this signal has a weak internal pull-down. if sdramc[bit 1]=1 and dram cache is not present in the system (indicated by cec[bit 5]=0, offset 53h), the cs4_64# function is selected. if dram cache is in the system or sdramc[bit 1] (offset 54h)=0, then krqak is used to drive the krqak function.
e 82439TX (mtxc) 13 preliminary 2.1.4. pci interface name type description ad[31:0] i/o 3.3/5v address/data. the standard pci address and data lines. address is driven with frame# assertion, data is driven or received in following clocks. c/be[3:0]# i/o 3.3/5v command/byte enable. the command is driven with frame# assertion, byte enables corresponding to supplied or requested data is driven on following clocks. frame# i/o 3.3/5v frame. assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. devsel# i/o 3.3/5v device select. this signal is driven by the mtxc when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o 3.3/5v initiator ready. asserted when the initiator is ready for a data transfer. trdy# i/o 3.3/5v target ready. asserted when the target is ready for a data transfer. stop# i/o 3.3/5v stop. asserted by the target to request the master to stop the current transaction. lock# i/o 3.3/5v lock. used to establish, maintain, and release resource locks on pci. req[3:0]# i 3.3/5v pci request. pci master requests for pci bus. gnt[3:0]# o 3.3v pci grant. permission is given to the master to use pci. phld# i 3.3/5v pci hold. this signal comes from the expansion bridge. it is the bridge request for pci. the mtxc will drain the dram write buffers, drain the cpu-to-pci posting buffers, and acquire the host bus before granting via phlda#. phlda# o 3.3v pci hold acknowledge. this signal is driven by the mtxc to grant pci to the expansion bridge. phlda# protocol has been modified to include support for passive release. par i/o 3.3/5v parity. a single parity bit is provided over ad[31:0] and c/be[3:0]. this signal should be pulled high through a weak external pull-up resistor. clkrun# i/o 3.3/5v clock run. an open drain output and also an input. mtxc requests the central resource (piix4) to start, or maintain the pci clock by the assertion of clkrun#. mtxc will tri-state clkrun# upon negation of reset (since clk is running upon negation of reset). external pull-up is required. note: this signal should be connected to the piix4 clkrun# pin. however, if it is left as a no connect on the mtxc, it must be pulled low through a 100 w (pull-down resistor. rst# i 3.3/5v reset. when asserted this signal asynchronously resets the mtxc. the pci signals also tri-state compliant to pci rev 2.0 and 2.1 specifications.
82439TX (mtxc) e 14 preliminary 2.1.5. test and clock name type description test# i 3.3/5v test in. nand tree mode is activated by driving this pin low. the test mode selected depends on the state of req[3:0]#. this pin should be pulled high with an external pull-up during normal operation. hclkin i 3.3/2.5v host clock in. this pin receives a buffered host clock. this clock is used by all of the mtxc logic that is in the host clock domain. pclkin i 3.3/5v pci clock in. this pin receives a buffered divide-by-2 host clock. this clock is used by all of the mtxc logic that is in the pci clock domain. 2.1.6. power management name type description susclk i 3.3v suspend clock. the signal is a 32 khz input for dram refresh circuitry and clocking events in suspend state. the dram refresh during suspend and non-suspend states is performed based on this clock. this signal has an internal pull-down resistor. susstat1# i 3.3v suspend status. susstat1# indicates mtxc?s power plane status during suspend mode. susstat1#, along with susclk and rst#, define the suspend protocol between mtxc and piix4. this signal has an internal pull-up resistor. 2.1.7. power and ground pi ns name type description v cc 3.3v main voltage supply. these pins are the primary voltage supply for the mtxc core and i/o periphery and must be connected to 3.3v. v cc (cpu) 3.3v or 2.5v cpu interface voltage supply. these pins are the primary voltage supply for the mtxc host periphery and must be connected to either 2.5v or 3.3v, depending on the voltage level of the cpu interface. refer to the power sequencing requirements section for additional details. v cc (sus) 3.3v suspend well voltage supply. these pins are the primary voltage supply for the mtxc suspend logic and i/o. if suspend to ram is supported, these pins should be on an isolated power plane; otherwise, they can be connected to the same 3.3v source used for the v cc pins. v cc 5ref 3.3v or 5v voltage reference. this pin is tied to 5v through a small external power sequencing circuit, if mtxc signals are required to be 5v tolerant. in a non 5v tolerant system (i.e. 3.3v only system), this signal can be tied directly to v cc . refer to the power sequencing requirements section for additional details. v ss 0v ground. these pins are the ground for the mtxc.
e 82439TX (mtxc) 15 preliminary 2.2. mtxc strapping options name type description scs a[31:30] secondary cache size. described in the cache control register bits 7:6. l2ramt a[29:28] initial l2 ram type. described in the cache control register bits 5:4. dram cache krqak dram cache l2 present upon reset negation. this bit is sampled to detect dram l2 cache. if sampled high, a dram cache is present. a weak pulldown is provided internally. a dram cache module should implement a pull-up on this pin that overrides the weak pulldown. bios does not have to be aware of this, this information is used by the mtxc to maintain optimal pburst timings. 25vd a26 2.5v voltage detection. this bit is used to determine the voltage level (3.3v or 2.5v) of the host clock connected to the host clock pin and the voltage on the v cc (cpu) pins. an external pull-down or pull-up resistor is required on this pin (pulled down for 2.5v and pulled up for 3.3v). hfd a27 frequency detection. bios can use this bit to determine if the system is 60 mhz (external pull-up) or 66 mhz (no strapping is present) as described in the drth register, bit 7. drth[bit 7] register is initialized with the inverted value of pin a27 upon reset negation. the a27 input buffer includes a weak pulldown resistor which will force drth[bit 7] to default to 1 if no strapping is present. 2.3. power planes the mtxc has three primary internal power planes. these power planes permit parts of the mtxc to power down to conserve battery life. table 1 shows the internal planes and their uses. table 1 . mtxc internal power planes power plane description signals powered v cc pins gnd pins suspend contains the logic needed to resume from the suspend-to-ram state. this power supply should be capable of providing a ? trickle ? current. the input signals attached to the suspend power plane do not support 5v input levels. these signals must not exceed v cc (sus). mwe#, mweb#, cke, ras[5:0]# 1 , cas[7:0]#, susclk, susstat1# v cc (sus) v ss cpu cpu interface signals have a separate supply so that the cpu interface can be 3.3v for existing cpus and can be 2.5v on future cpus. a[31:3], be[7:0]#, ads#, brdy#, na#, ahold, eads#, boff#, hitm#, m/io#, d/c#, w/r#, hlock#, cache#, ken#/inv, smiact#, hd[63:0], hclkin v cc (cpu) v ss v cc 5ref the v cc 5ref signal provides protection for the 5v tolerant 3.3v signals. pci bus input and i/o, md[63:0], tio[7:0], pclkin, test# v cc 5ref v ss main contains all the rest of the mtxc logic. this plane is powered by the main system power supply. all other signal pins v cc v ss
82439TX (mtxc) e 16 preliminary notes: 1. krqak is not part of the suspend well. when this pin is used as the 5 th ras line (cs4_64), special considerations must be taken. 2.4. power sequencing requirements the v cc 5ref signal must be tied to 5v in a system requiring 5v tolerance. in a 5v tolerant system, v cc 5ref must power up before or simultaneous to v cc . it must power down after or simultaneous to v cc . at any time, v cc 5ref should not be more than 0.6 volts below v cc . in a non-5v tolerant system (3.3v only), this signal can be tied directly to v cc . in this case, there are no sequencing requirements. refer to figure 2 for an example circuit schematic which may be used to ensure the proper v cc 5ref sequencing. v c c s u p p l y ( 3 . 3 v ) 5 v s u p p l y 1 k w 1 u f t o s y s t e m v r e f t o s y s t e m pwr_seq figure 2 . example v cc 5ref sequencing circuit the v cc (cpu) power plane is tied to either 2.5 volts or 3.3 volts, depending on the voltage level of the cpu interface. in a system that ties this power plane to 2.5 volts, the v cc (cpu) pins must power up after or simultaneous to v cc . it must power down before or simultaneous to v cc . at any time, v cc should not be more than 1.2 volts below the v cc (cpu) plane.
e 82439TX (mtxc) 17 preliminary 2.5. signal states during and after a hard reset table 2 shows the state of all the mtxc output and bi-directional signals when rst# is asserted. an undefined state means that the signal is driven either high or low, but not tri-stated. table 2 . signal states during/after reset name state during rst# state after rst# a[31:3] low tri-state brdy# high high na# high high ahold high low eads# high high boff# high high ken#/inv low low hd[63:0] tri-state tri-state ras[5:0]# or cs[5:0]# undefined high cas[7:0]# or dqm[7:0] undefined undefined ma[11:0], ba1,ma13 undefined undefined mwe#, mweb# high high sras[a,b]# high high scas[a,b]# high high cke,ckeb undefined high md[63:0] tri-state tri-state cadv# high high cads# high high table 2 . signal states during/after reset name state during rst# state after rst# ccs# low low coe# high high gwe# high high bwe# high high tio[7:0] low tri-state twe# low high krqak input input ad[31:0] low tri-state c/be[3:0]# low tri-state frame# tri-state tri-state devsel# tri-state tri-state irdy# tri-state tri-state trdy# tri-state tri-state stop# tri-state tri-state lock# tri-state tri-state gnt[3:0]# tri-state high phlda# high high par low undefined clkrun# tri-state tri-state
82439TX (mtxc) e 18 preliminary 3. 0. register descr iption the mtxc contains two sets of software accessible registers (i/o mapped and pci configuration registers), accessed via the host cpu i/o address space. the i/o mapped registers control access to pci configuration space. configuration registers residing in pci configuration space used to specify pci configuration, dram configuration, cache configuration, operating parameters and optional system features. the mtxc internal registers (both i/o mapped and pci configuration registers) are only accessible by the host cpu and cannot be accessed by pci masters. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of confadd, which can only be accessed as a dword. all multi-byte numeric fields use ? little-endian ? ordering (i.e., lower addresses contain the least significant parts of the field). the following nomenclature is used for access attributes: ro read only . if a register is read only, writes to this register have no effect. r/w read/write . a register with this attribute can be read and written. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. some of the mtxc registers described in this section contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. in addition to reserved bits within a register, the mtxc contains address locations in the pci configuration space that are marked ? reserved ? ( table 3 ). the mtxc responds to accesses to these address locations by completing the host cycle and returning a value of zero. the registers marked as ? undefined ? will return a non- zero value and are defined as read only. software should not write to reserved or undefined mtxc configuration locations in the device-specific region (above address 3fh). upon reset, the mtxc sets its internal configuration registers to predetermined default states. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the dram configurations, cache configuration, operating parameters and optional system features that are applicable, and to program the mtxc registers accordingly. 3.1. i/o mapped registers the mtxc contains three registers that reside in the cpu i/o address space ? the configuration address (confadd) register, the configuration data (confdata) register, and the pm2 register block. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window.
e 82439TX (mtxc) 19 preliminary 3.1.1. pm2_cntrl ? ? pm2 register block i/o address: 0022h default value: 00h access: read/write bit descriptions 7:1 reserved. 0 arbiter disable (arb_dis) . . when arb_dis=1, the mtxc does not respond to any req# signals (including phold#) going active until this bit is set back to 0. this bit is used to disable bus master accesses prior to placing the cpu in a stop clock state. this bit maintains cache coherency by preventing pci masters from gaining access to the pci bus and causing snoop cycle activity. mctl[bit 6] (offset 79h) must be set to 1 before this register is accessible. 3.1.2. confadd ? ? configuration address register i/o address: 0cf8h (accessed as a dword) default value: 00000000h access: read/write confadd is a 32-bit register accessed only when referenced as a dword. a byte or word reference will ? pass through ? the configuration add ress register onto the pci bus. the confadd register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. bit descriptions 31 configuration enable (cone). 1=enable. 0=disable. 30:24 reserved. 23:16 bus number. when the bus number is programmed to 00h the target of the configuration cycle is either the mtxc or the pci local bus that is directly connected to the mtxc, depending on the device number field. a type 0 configuration cycle is generated on pci if the bus number is programmed to 00h and the mtxc is not the target. if the bus number is non-zero a type 1 configuration cycle is generated on pci with the bus number mapped to ad[23:16] during the address phase. 15:11 device number. this field selects one agent on the pci bus selected by the bus number. during a type 1 configuration cycle this field is mapped to ad[15:11]. during a type 0 configuration cycle this field is decoded and one of ad[31:11] is driven to a 1. the mtxc is always device number 0. 10:8 function number. this field is mapped to ad[10:8] during pci configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the mtxc responds to configuration cycles with a function number of 000b; all other function number values attempting access to the mtxc (device number=0, bus number=0) will generate a type 0 configuration cycle onto the pci bus with no idsel asserted, which will result in a master abort. 7:2 register number. this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to ad[7:2] during pci configuration cycles. 1:0 reserved.
82439TX (mtxc) e 20 preliminary 3.1.3. confdata ? ? configuration data register i/o address: 0cfch default value: 00000000h access: read/write confdata is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by confdata is determined by the contents of confadd. bit descriptions 31:0 configuration data window (cdw). if bit 31 of confadd is 1, any i/o reference that falls in the confdata i/o space is mapped to configuration space using the contents of confadd. pci configuration space mapped registers the pci bus defines a slot based ? configuration space ? that allows each device to contain up to 256 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space ? configuration read and configuration write . while memory and i/o spaces are supported by the pentium microprocessor, configuration space is not supported. the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. the mtxc supports only mechanism #1. the bus cycles used to access mtxc internal configuration registers are described later in the pci cycle timings section. the configuration access mechanism makes use of the confadd register and confdata register. to reference a configuration register, a dword i/o write cycle is used to place a value into confadd that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. confadd[31] must be 1 to enable a configuration cycle. confdata then becomes a window onto four bytes of configuration space specified by the contents of confadd. any read or write to confdata will result in the mtxc translating confadd into a pci configuration cycle. type 0 access if the bus number field of confadd is 0 a type 0 configuration cycle is performed on pci. confadd[10:2] is mapped directly to ad[10:2]. the device number field of confadd is decoded onto ad[31:11]. the mtxc is device #0 and does not pass its configuration cycles to pci so ad11 will never be asserted. device #1 will assert ad12, device #2 will assert ad13, and so forth up to device #20 which will assert ad31. only one ad line is asserted at a time. all device numbers higher than 20 cause a type 0 configuration access with no idsel asserted, which will result in a master abort. type 1 access if the bus number field of confadd is non-zero a type 1 configuration cycle is performed on pci. confadd[23:2] is mapped directly to ad[23:2]. ad[1:0] are driven to 01 to indicate a type 1 configuration cycle. all other lines are driven to 0.
e 82439TX (mtxc) 21 preliminary table 3 . mtxc configuration space address offset register symbol register name access pci specific registers 00 - 01h vid vendor identification ro 02 - 03h did device identification ro 04 - 05h pcicmd pci command register r/w 06 - 07h pcists pci status register ro, r/wc 08 rid revision identification ro 09 - 0bh classc class code ro 0ch ? reserved ? 0dh mlt master latency timer r/w 0eh hedt header type ? 0fh bist bist register r/w 10 - 3fh ? reserved ? mtxc specific registers 40 - 4eh ? reserved ? 4fh acon arbitration control r/w 50h pcon pci control r/w 51h ? reserved ? 52h cc cache control r/w 53 cec extended cache control r/w 54 - 55h sdramc sdram control rw 56h dramec dram extended control r/w 57h dramc dram control r/w 58h dramt dram timing r/w 59 ? 5fh pam[6:0] programmable attribute map (7 registers) r/w 60 ? 65h drb[5:0] dram row boundary (6 registers) r/w 66h ? reserved ? 67h drth dram row type high r/w 68h drtl dram row type low r/w
82439TX (mtxc) e 22 preliminary table 3 . mtxc configuration space address offset register symbol register name access 69 ? 6ah ? undefined ro 6b ? 6fh ? reserved ? 70h mtt multi-transaction timer r/w 71h esmramc extended system management ram control r/w 72h smramc system management ram control r/w 73h ? reserved ? 74h ? undefined ro 76 - 78h ? reserved ? 78h ? undefined ro 79 mctl miscellaneous control register r/w 7a - fch ? reserved ? fdh ? undefined ro fe - ffh ? reserved ?
e 82439TX (mtxc) 23 preliminary 3.1.4. vid ? ? vendor identification register address offset: 00 ? 01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . . this is a 16-bit value assigned to intel. 3.1.5. did ? ? device identification register address offset: 02 ? 03h default value: 7100h attribute: read only this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . . this is a 16 bit value assigned to the mtxc. 3.1.6. pcicmd ? ? pci command register address offset: 04 ? 05h default: 06h access: read/write this 16-bit register provides basic control over the mtxc?s ability to respond to pci cycles. the pcicmd register in the mtxc enables and disables the assertion of serr# and pci master accesses to main memory. bit description 15:10 reserved . 9 fast back-to-back (fb2b). (not implemented) this bit is hardwired to 0. 8 serr# enable (serre) . . (not implemented) this bit is hardwired to 0. 7 address/data stepping . . (not implemented) this bit is hardwired to 0. 6 parity error enable (perre) . . (not implemented) this bit is hardwired to 0. 5 video pallet snooping (vps) . . (not implemented) this bit is hardwired to 0. 4 memory write and invalidate enable (mwie) . . (not implemented) this bit is hardwired to 0. the mtxc will never use the memory write and invalidate pci command. 3 special cycle enable (sce) . . (not implemented) this bit is hardwired to 0, as the mtxc does not respond to pci special cycles.
82439TX (mtxc) e 24 preliminary bit description 2 bus master enable (bme) . . (not implemented) this bit is hardwired to 1. the mtxc does not support disabling of its bus master capability on the pci bus. 1 memory access enable (mae) . . when mae=1, the mtxc permits pci masters to access main memory if the pci address selects enabled dram space. when mae=0, the mtxc does not respond to main memory accesses. 0 i/o access enable (ioae) . . (not implemented) the mtxc does not respond to pci i/o cycles. this bit is hardwired to 0. 3.1.7. pcists ? ? pci status register address offset: 06 ? 07h default value: 0200h access: read only, read/write clear pcists is a 16-bit status register that reports the occurrence of a pci master abort and pci target abort. pcists also indicates the devsel# timing that has been set by the mtxc hardware. bit description 15 detected parity error (dpe). this bit is hardwired to 0, as pci received parity checking is not implemented by the mtxc. 14 signaled system error (sse). this bit is hardwired to 0 as mtxc does not support serr#. 13 received master abort status (rmas). when the mtxc terminates a host-to-pci transaction (mtxc is a pci master) with an unexpected master abort, this bit is set to 1. note that master abort is the normal and expected termination of pci special cycles. software resets this bit to 0 by writing a 1 to it. 12 received target abort status (rtas). when a mtxc-initiated pci transaction is terminated with a target abort, rtas is set to 1. software resets rtas to 0 by writing a 1 to it. 11 signaled target abort status (stas). this bit is hardwired to 0, as the mtxc never terminates a pci cycle with a target abort. 10:9 devsel# timing (devt) . . this 2-bit field indicates the timing of the devsel# signal when the mtxc responds as a target, and is hardwired to the value 01b (medium) to indicate the slowest time that devsel# is generated. 8 data parity detected (dpd) . . this bit is hardwired to 0, as perr# is not implemented. 7 fast back-to-back (fb2b). this bit is hardwired to 0, as fast back to back cycle generation is not implemented. 6 user defined format (udf). this bit is hardwired to 0. this is because the mtxc does not contain any configurations that depend on the environment, such as network frequencies. 5 66-mhz pci capable (66c). this bit is hardwired to 0. the mtxc does not interface to 66-mhz pci. 4:0 reserved .
e 82439TX (mtxc) 25 preliminary 3.1.8. rid ? ? revision identification register address offset: 08h default value: 01h access: read only this register contains the revision number of the mtxc. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number. this is an 8-bit value that indicates the revision identification number for the mtxc. 3.1.9. classc ? ? class code register address offset: 09 - 0bh default value: 00h access: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the mtxc. this register also contains the base class code and the function sub-class in relation to the base class code. bit description 23:16 base class code (basec). 06=bridge device. 15:8 sub-class code (scc). 00h=host bridge. 7:0 programming interface (pi). 00h=hardwired as a host-to-pci bridge. 3.1.10. mlt ? ? master latency timer register address offset: 0dh default value: 00h access: read/write mlt is an 8-bit register that controls the amount of time the mtxc, as a bus master, can burst data on the pci bus. the count value is an 8-bit quantity. however mlt[2:0] are reserved and assumed to 0 when determining the count value. mlt is used to guarantee the host cpu a minimum amount of the system resources. the number of clocks programmed in the mlt represents the guaranteed time slice (measured in pci clocks) allotted to the mtxc, after which it must surrender the bus as soon as other pci masters request the bus. the default value of mlt is 00h or 0 pci clocks. bit description 7:3 master latency timer count value 2:0 reserved. read as 0s
82439TX (mtxc) e 26 preliminary 3.1.11. hedt ? ? header type register address offset: 0eh default value: 00h access: read only this register contains the header type of the mtxc. this code is 00h indicating that the mtxc?s configuration space map follows the basic format. bit description 7:0 device type (devicet). 00h=indicates a basic configuration space format. 3.1.12. bist ? ? bist register address offset: 0fh default value: 00h access: read/write the built in self test (bist) function is not supported by the mtxc. writes to this register have no effect. bit description 7 bist supported . . this read only bit is always set to 0, disabling the bist function. writes to this bit position have no effect. 6 start bist . . this function is not supported and writes have no effect. 5:4 reserved . 3:0 completion code . . this read only field always returns 0 when read and writes have no effect. 3.1.13. acon ? ? arbitration control register address offset: 4fh default value: 00h access: read/write the acon register enables and disables features related to pci arbitration and pci 2.1 compliance. bit description 7 extended cpu-to-piix4 phlda# signaling enable (xplde). when xplde=1, the mtxc adds the following additional signaling to signal phlda# (i.e., in addition to the normal cpu/piix4 phold/phlda# protocol): 1. whenever the north bridge begins a pci read/write transaction, it will assert phlda# for 1 pclk within the address phase of the transaction. 2. if the cpu is attempting a locked cycle and lock has been established (i.e. plock# was seen negated in address phase), the phlda# remains asserted for one additional clock following the address phase. this bit should be set to 1 anytime both passive release and delayed transaction are enabled in the piix4. passive release and delayed transaction are enabled via bits 1 and 0 in piix4 register 82h (function 0). when bit 7 in this register is set to 1 (enabled), bit 7 in piix4 register, 6a (function 0) must also be set to 1. when enabling these two bits, enable bit 7 in the piix4 first, followed by bit 7 in this register. when disabling these two bits, disable bit 7 in this register first, followed by bit 7 in the piix4. 6:0 reserved.
e 82439TX (mtxc) 27 preliminary 3.1.14. pcon ? ? pci control register address offset: 50h default value: 00h access: read/write the pcon register enables and disables features related to the pci bus that are not already covered in the required pci space. bit description 7:4 reserved. 3 pci concurrency enable (pce). 1=cpu can access dram and l2 while a non-piix4 pci master is targeting peer pci devices. 0 (default)=cpu is held off of the bus during all pci master cycles. this bit should be set to 1 by bios during normal operation . 2:0 reserved. 3.1.15. cc ? ? cache control register address offset: 52h default value: ssss0010 (s=strapping option) access: read/write this 8-bit register defines the secondary cache operations. the cc register enables and disables the second level cache, adjusts cache size, selects the cache write policy, selects the caching policy when cache# is negated on reads, informs the mtxc how the srams are connected, and defines the cache sram type. after a hard reset, cc[7:4] reflect the signal levels on the host address lines a[31:28]. bit description 7:6 secondary cache size (scs) . . this field reflects the inverted signal level on the a[31:30] pins at the rising edge of the reset signal. the options are: bits[7:6] secondary cache size 00 cache not populated 01 256 kbytes 10 512 kbytes 11 reserved the reset values can be overwritten with subsequent writes to the cc register. note 1. when bits[7:6]=00, the secondary cache is disabled. 2. when bits[7:6] 1 00, the flce bit must also be set to 1 (l2 cache cannot be enabled unless the l1 cache is also enabled).
82439TX (mtxc) e 28 preliminary bit description 5:4 l2 sram type (l2sramt) . . this field reflects the inverted signal level on the a[29:28] pins at the rising edge of the reset signal. the reset values can be overwritten with subsequent writes to the cc register. the options are: bits[5:4] sram type 00 pipelined burst sram 01 reserved 10 reserved 11 two banks of pipelined burst note when 512-kb pipelined burst sram l2 mode is selected (via scs and sramt), ccs# is negated after na# is asserted, and reasserted after a pipelined ads# is detected. cads# is asserted along with the final brdy# for a cycle if a pipelined cycle is outstanding (i.e., an ads# was detected). 3 na disable (nad). 1=disable. 0=enable. when disabled, mtxc never asserts the na# pin. when enabled, na# assertion is dependent on the cache type and size selected (via sramt, scs). note that nad must be set to 1 if the na# pin of the mtxc is not connected to the processor. this bit should be set to 0 for normal operation in systems that connect na# to the processor. 2 reserved. 1 secondary cache force miss or invalidate (scfmi) . . when set to a 1, the l2 hit/miss detection is disabled, and all tag lookups result in a miss. if the l2 is enabled, then the cycle is processed as a miss (as described in chapter 4.2). if the l2 is populated but disabled (flce=0), then when scfmi is set to a 1, any cpu read cycle will invalidate the selected tag entry. when scfmi is set to a 0, normal l2 cache hit/miss detection and cycle processing occurs. software can flush the cache (cause all modified lines to be written back to dram) by setting scfmi to a 1 with the l2 enabled (non-zero scs, flce=1), and reading all l2 cache tag address locations. see flce bit description for flce/scfmi interaction. 0 first level cache enable (flce) . . 1=enable. 0=disable. when flce=1, the mtxc responds to cpu cycles with ken# asserted for cacheable memory cycles. when flce=0, ken# is always negated. this prevents new cache line fills to either the first level or second level cache. the flce/scfmi interaction is summarized below. note that ? normal l2 operation ? is further dependent on the scs field programming. flce scfmi l2 result 0 0 l2 disabled 0 1 l2 disabled, mtxc tag invalidate on reads 1 0 normal l2 operation (dependent on scs) 1 1 l2 enabled, mtxc miss forced on reads/writes (note that writes to the c ache are also forced as misses, making it possible to create incoherent dram/l2 data.)
e 82439TX (mtxc) 29 preliminary 3.1.16. cec ? ? extended cache control register address offset: 53h default value: 14h access: read/write, read only this 8-bit register defines the refresh rate (in hclks) for a dram cache l2 cache implementation, if enabled. bit description 7:6 reserved 5 dram cache l2 present (ml2) ? ? ro. when ml2=1, an l2 dram cache is present. 4:0 dram cache l2 refresh timer (mcrt) ? ? r/w. these bits determine the time the mtxc remains idle during a dram cache refresh sequence. the smallest value for the mrct must be 04h; otherwise, the mtxc will not function properly . the default value sets the timer refresh to 20 hclks. 3.1.17. sdramc ? ? sdram control register address offset: 54 ? 55h default value: 0000h access: read/write bit description 15:9 reserved. 8:6 special sdram mode select (ssms). these bits select 1 of 4 special sdram modes for testing and initialization. note that the nop command must be programmed first before any other command can be issued. after the dram detection process has completed, bits[7:5] must remain at ? 000 ? during normal dram operation. bits[8:6] mode 000 normal sdram mode (default). 001 nop command enable (nopce). this mode forces all cpu cycles to dram to generate a sdram nop command on the memory interface. 010 all banks precharge command enable (abpce). this setting enables a mode where all cpu cycles to dram are converted to an all banks precharge command on the memory interface. used for bios detection algorithm. 011 mode register command enable (mrce). this setting enables a mode where all cpu cycles to dram are converted into mrs commands to the memory interface. the command is driven on the ma[11:0] lines. ma[2:0] needs to be always driven to 010 for burst of 4 mode. ma3 needs to be always driven to 1 for interleave wrap type mode. ma4 needs to be driven to the value in the cas# latency bit. ma[6:5] needs to be always driven to 01. ma[11:7] needs to be always driven to 00000. the bios will select an appropriate host address for each row of memory such that the right commands are generated on the memory address ma[11:0] lines. the bios needs to be cognizant of the mapping of the host addresses to memory addresses. e.g. a host address of 1d0h will set up the mode registers in row 0 of sdram with burst length of 4, wrap type of interleaved, and cas latency of 3. 100 cbr cycle enable (cbrc). this setting enables a mode where all cpu cycles to dram are converted to sdram cbr refresh cycles on the memory interface. 101 reserved 11x reserved
82439TX (mtxc) e 30 preliminary bit description 5 ras# to cas# override (rco) . . when set to 1, and the cl bit (cas latency) is 0 (cas latency=3), then a ras# to cas# delay of 2 hclks is provided for sdram . when set to 0, a ras# to cas# delay for sdram is determined by the cl bit . 4 cas# latency (cl). when set to 1, a cas# latency of 2 is used for all sdram cycles. when reset to 0, cas# latency of 3 is used for all sdram cycles. 3 ras# timing (rt). this bit controls ras# precharge, ras# active to precharge time and refresh to ras# active delay (in hclks): bit 3 ras# ras# act. refresh to precharge to precharge ras# act. 0 3 5 8 1 3 4 7 2 reserved. 1 64-mbit technology enable (64mten). 1=enable. 0=disable. when set to 0, the mtxc does not support 64-mbit sdram devices. in this mode, the mtxc supports 4-mbit, 16-mbit, and 64-mbit technology for edo/fpm systems and 4 mbit and 16 mbit for sdram systems (i.e., 64 mbit not supported in sdram systems). when set to 1, the mtxc supports 4 mbit, 16 mbit, and 64 mbit for both sdram and edo/fpm devices. in this mode, the ras#/cs5# signal becomes ras#/cs5#/ma13, ras4#/cs4# becomes ras4#/cs4#/ba1, and krqak/cs4_64# becomes cs4_64#. cs4_64# (fifth row) function is provided if this signal is set to 1 and dram cache is not present in the system (indicated by a 0 in bit 5, register 53h). 0 reserved. table 4 lists the cas# latency, ras# to cas#, ras# precharge, ras# active to precharge and refresh to ras# active programmable timings. table 4 . programming timings operating frequency cas latency (cl) ras# to cas# (trcd) ras# precharge (trp) ras# active to precharge (tras) refresh to ras# (trc) register 54h bits[5:3] 60/66 mhz 3 hclks 3 hclks 3 hclks 5 hclks 8 hclks 000 60/66 mhz 3 hclks 2 hclks 3 hclks 5 hclks 8 hclks 100 60/66 mhz 2 hclks 2 hclks 3 hclks 4 hclks 7 hclks 011
e 82439TX (mtxc) 31 preliminary 3.1.18. dramec ? ? dram extended control register address offset: 56h default value: 52h access: read/writ e this 8-bit register contains additional controls for main memory dram operating modes and features. bit description 7 reserved. 6 refresh ras# assertion(rra). 1=5 clocks (ras# asserted for refresh cycles). 0=4 clocks. 5 fast edo lead off (felo). 1=enables fast timing edo read cycles. 0=disable. this is valid for edo drams only (in both a synchronous cache and a cacheless system). this result is a 1 hclk pull-in for all read leadoff latencies for edo drams. (i.e., page hits, page misses, and row misses). this bit must be 0 if any of the dram rows is populated with fpm drams. 4 speculative lead off (sld). if set to 0, the dram controller read request is presented before the final memory target (cache/dram/pci) has been decoded by the mtxc. this results in a 1 hclk pull-in for all read leadoff latencies. note that if the cycle does not actually target dram, the dram cycle is later terminated. the sld bit applies to edo/fpm and sdram . this bit should be set to 1 in systems with a l2 cache and to 0 for systems without a l2 cache 3 reserved. 2:1 memory address drive strength (mad). this field controls the strength of the output buffers driving the ma, srasx#, scasx#, mwex# and ckex pins. it is recommended that series termination or undershoot and overshoot diodes be used on these lines. bit[2:1] ma[13,11:0], ba1 sras[a,b],scas[a,b], mwex#, ckex 00 10 ma 10 ma 01 10 ma 16 ma 10 16 ma 10 ma 11 16 ma 16 ma setting memory address drive strength: 1 row 2 row 3 row 4 row 5 row 6 row 00 00 11 11 11 01* * assuming all rows are buffered 0 reserved.
82439TX (mtxc) e 32 preliminary 3.1.19. dramc ? ? dram control register address offset: 57h default value: 01h access: read/write this 8-bit register controls main memory dram operating modes and features. bit description 7:6 hole enable (hen). this field enables a memory hole in dram space. cpu cycles matching an enabled hole are passed on to pci. pci cycles matching an enabled hole will be ignored by the mtxc (no devsel#). note that a selected hole is not remapped. bits[7:6] hole en abled 00 none 01 512 kb - 640 kb (128 kbytes) 10 15 mb - 16 mb (1 mbyte) 11 14 mb - 16 mb (2 mbytes) 5 reserved. 4 enhanced paging disable (epd). 1=mtxc keeps page open until a page/row miss. when epd=0, the mtxc uses additional information to keep the dram page open when the host may be ? right back ? . see dram section for additional information. this bit should be set to 0 for normal operation. 3 edo detect mode enable (edme). 1=enables a special timing mode for bios to detect edo dram type on a bank-by-bank basis. once all dram row banks have been tested for edo, the edme bit should be set to 0. otherwise, performance will be seriously impacted. 2:0 dram refresh rate (drr). the dram refresh rate for ? fpm/edo only ? dram subsystem is adjusted according to the value selected by this field. dram refresh is implemented using susclk. bits[2:0] dram refresh rate 000 refresh disabled (results in the eventual loss of dram data) 001 15.6 s 010 31.2 s (for edo/fpm only memory subsystem) 011 64.4 s (for edo/f pm only memory subsystem) 100 125 s (for edo/fpm only memory subsystem) 101 256 s (for edo/fpm only memory subsystem) 110 reserved 111 reserved notes 1. if any of the row is populated with sdrams, this field must be set to 15.6 s refresh rate. 2. selecting refresh rate of 125 s or 256 s may violate the max ras# active time dram specification. it is up to the system designer to make sure this does not happen.
e 82439TX (mtxc) 33 preliminary 3.1.20. dramt ? ? dram timing register address offset: 58h default value: 00h access: read/ write this 8-bit register controls main memory dram timings. for sdram specific timing control, see the sdramc timing register definition. bit description 7 reserved. 6:5 dram read burst timing (drbt). the dram read burst timings are controlled by the drbt field. slower rates may be required in certain system designs to support loose layouts or slower memories. most system designs will be able to use one of the faster burst mode timings. the timing used depends on the type of dram on a per-bank basis, as indicated by the drt register. the x322 timings for edo burst rate should be used only when the fast edo path select (feps) bit is set to 1 and the timings for the edo burst rate for x222 have a negative margin. this forces the mxs to be negated after the leadoff; thus, selecting the fast path for the leadoff and the slow path for the burst cycles. when feps=1 and the edo burst rate is set to x222, the edo read cycle is selected through the fast path for both leadoff and the burst cycles. when feps=0 and the edo burst rate is set to x222, the edo read cycle is selected through the slow path for both leadoff and the burst cycles. drbt edo burst rate fpm burst rate 00 x444 x444 01 x333 x444 10 x222 x333 11 reserved reserved 4:3 dram write burst timing (dwbt). the dram write burst timings are controlled by the dwbt field. slower rates may be required in certain system designs to support loose layouts or slower memories. most system designs will be able to use one of the faster burst mode timings. dwbt e do/fpm burst rate dwbt edo/fpm burst rate 00 x444 10 x222 01 x333 11 reserved 2 reserved.
82439TX (mtxc) e 34 preliminary bit description 1:0 dram leadoff timing (dlt) . . the dram leadoff timings are controlled by the dlt bits. slower leadoffs may be required in certain system designs to support loose layouts or slower memories. the row miss leadoff timings are summarized below for edo/fpm reads and writes. changing dlt affects the row miss and page miss timings only (e.g., dlt=01 is one clock faster than dlt=00 on row miss and page miss timings). these bit control ma setup to cas# assertion. dlt does not affect page hit timings. thus, dlt=00 or dlt=01 has same page hit timings for reads and writes (e.g., for reads, it would be 10-3=7 clocks for dlt=00 or dlt=01) dlt read leadoff write leadoff ras# precharge ras-to-cas delay 00 11 7 3 4 01 10 6 3 3 10 11 7 4 4 11 10 6 4 3 sld and felo bits have cumulative effect on the leadoff timings. the above leadoff represent timings with sld=1 and felo=0. 3.1.21. pam ? ? programmable attribute map registers (pam[6:0]) address offset: 59h (pam0) (5fh (pam6) default value: 00h attribute: read/write size: 8 bits (each register) the mtxc allows programmable memory and cacheability attributes on 14 memory segments of various sizes in the 640-kbytes to 1-mbyte address range. seven programmable attribute map (pam) registers are used to support these features. three bits are used to specify l1 cacheability and memory attributes for each memory segment. these attributes are: re read enable . when re=1, the cpu read accesses to the corresponding memory segment are directed to main memory. conversely, when re=0, the cpu read accesses are directed to pci. we write enable . when we=1, the cpu write accesses to the corresponding memory segment are directed to main memory. conversely, when we=0, the cpu write accesses are directed to pci. ce cache enable . when ce=1, the corresponding memory segment is l1 cacheable. ce must not be set to 1 when re is reset to 0 for any particular memory segment. when ce=1 and we=0, the corresponding memory segment is cached in the first level cache only on cpu code read cycles. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. the characteristics for memory segments with these read/write attributes are described in table 5 .
e 82439TX (mtxc) 35 preliminary table 5 . attribute definition read/write attribute definition read only read cycles: cpu cycles are serviced by the dram in a normal manner. write cycles: cpu initiated write cycles are ignored by the dram interface as well as the cache. instead, the cycles are passed to pci for termination. areas marked as read only are l1 cacheable for code accesses only. these regions are not cached in the second level cache. write only read cycles: all read cycles are ignored by the dram interface as well as the second level cache. cpu-initiated read cycles are passed onto pci for termination. the write only state can be used while copying the contents of a rom, accessible on pci, to main memory for shadowing, as in the case of bios shadowing. write cycles: cpu write cycles are serviced by the dram and l2 cache in a normal manner. read/write this is the normal operating mode of main memory. both read and write cycles from the cpu and pci are serviced by the dram and l2 cache interface. disabled all read and write cycles to this area are ignored by the dram and cache interface. these cycles are forwarded to pci for termination. each pam register controls two regions, typically 16 kbytes in size. each of these regions has a 4-bit field. the four bits that control each region have the same encoding and are defined in table 6 . pci master access to dram space is also controlled by the pam registers. if the pam programming indicates a region is writeable, then pci master writes will be accepted (devsel# generated). if the pam programming indicates a region is readable, pci master reads will be accepted. if a pci write to a non-writeable dram region, or a pci read to a non-readable dram region is seen, the mtxc will not accept the cycle (devsel# will not be asserted). pci master accesses to enable memory hole regions will not be accepted. table 6 . attribute bit assignment bits [7, 3] reserved bits [6, 2] cache enable bits [5, 1] write enable bits [4, 0] read enable description x x 0 0 dram disabled, accesses directed to pci x 0 0 1 read only, dram write protected, non-cacheable x 1 0 1 read only, dram write protected, l1 cacheable for code accesses only x 0 1 0 write only x 0 1 1 read/write, non-cacheable x 1 1 1 read/write, cacheable as an example, consider a bios that is implemented on the expansion bus. during the initialization process the bios can be shadowed in main memory to increase the system performance. when a bios is shadowed in main memory, it should be copied to the same address location. to shadow the bios, the attributes for that address range should be set to write only. the bios is shadowed by first doing a read of that address. this read is forwarded to the expansion bus. the cpu then does a write of the same address, which is directed to main
82439TX (mtxc) e 36 preliminary memory. after the bios is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. table 7 . pam register and associated memory segments pam reg. attribute bits memory segment comments offset pam0[3:0] reserved 59h pam0[7:4] r ce we re 0f0000h ? 0fffffh bios area 59h pam1[3:0] r ce we re 0c0000h ? 0c3fffh isa add-on bios 5ah pam1[7:4] r ce we re 0c4000h ? 0c7fffh isa add-on bios 5ah pam2[3:0] r ce we re 0c8000h ? 0cbfffh isa add-on bios 5bh pam2[7:4] r ce we re 0cc000h ? 0cffffh isa add-on bios 5bh pam3[3:0] r ce we re 0d0000h ? 0d3fffh isa add-on bios 5ch pam3[7:4] r ce we re 0d4000h ? 0d7fffh isa add-on bios 5ch pam4[3:0] r ce we re 0d8000h ? 0dbfffh isa add-on bios 5dh pam4[7:4] r ce we re 0dc000h ? 0dffffh isa add-on bios 5dh pam5[3:0] r ce we re 0e0000h ? 0e3fffh bios extension 5eh pam5[7:4] r ce we re 0e4000h ? 0e7fffh bios extension 5eh pam6[3:0] r ce we re 0e8000h ? 0ebfffh bios extension 5fh pam6[7:4] r ce we re 0ec000h ? 0effffh bios extension 5fh notes: the ce bit should not be changed while the l2 cache is enabled.
e 82439TX (mtxc) 37 preliminary dos application area (00000h ? 9fffh) read, write, and cacheability attributes are always enabled and are not programmable for the 0 ? 640-kbytes dos application region. video buffer area (a0000h ? bffffh) this 128-kbytes area is not controlled by attribute bits. cpu-initiated cycles in this region are always forwarded to pci for termination. this area is not cacheable. expansion area (c0000h ? dffffh) this 128-kbytes area is divided into eight 16-kbytes segments. each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled memory that is disabled is not remapped. cacheability status can also be specified for each segment. extended system bios area (e0000h ? effffh) this 64-kbytes area is divided into four 16-kbytes segments. each segment can be assigned independent cacheability, read, and write attributes. memory segments that are disabled are not remapped elsewhere. system bios area (f0000h ? fffffh) this area is a single 64-kbytes segment. this segment can be assigned cacheability, read, and write attributes. when disabled, this segment is not remapped. extended memory area (100000h ? ffffffffh) the extended memory area can be split into several parts: flash bios area from 4 gbytes to 4 gbytes ? 512 kbytes (aliased on isa at 16 mbytes ? 15.5 mbytes) dram memory from 1 mbytes to a maximum of 512 mbytes pci memory space from the top of dram to 4 gbytes ? 512 kbytes on power-up or reset the cpu vectors to the flash bios area, mapped in the range of 4 gbytes to 4 gbytes ? 512 kbytes. this area is physically mapped on the expansion bus. since these addresses are in the upper 4- gbytes range, the request is directed to pci. the dram memory space can occupy extended memory from a minimum of 1 mbytes up to 256 mbytes. this memory is cacheable. pci memory space from the top of main memory to 4 gbytes is always non-cacheable.
82439TX (mtxc) e 38 preliminary 3.1.22. drb ? ? dram row boundary registers address offset: 60 ? 65h default value: 02h access: read/write the mtxc supports 6 rows of dram. each row is 64-bits wide. the dram row boundary registers define upper and lower addresses for each dram row. contents of these 8-bit registers represent the boundary addresses in 4-mbytes granularity. drb0=total amount of memory in row 0 (in 4 mbytes) drb1=total amount of memory in row 0 + row 1 (in 4 mbytes) drb2=total amount of memory in row 0 + row 1 + row 2 (in 4 mbytes) drb3=total amount of memory in row 0 + row 1 + row 2 + row 3 (in 4 mbytes) drb4=total amount of memory in row 0 + row 1 + row 2 + row 3 + row 4 (in 4 mbytes) drb5=total amount of memory in row 0 + row 1 + row 2 + row 3 + row 4 + row 5 (in 4 mbytes) the dram array can be configured with 512-kb, 1-mb, 4-mb, or 16-mb deep by 32- or 36-bit wide simms. each register defines an address range that will cause a particular ras# line to be asserted (e.g., if the first dram row is 8 mbytes, accesses within the 0 to 8-mbytes range will cause ras0# to be asserted). note when programming the drb registers, the following programming consideration must be followed: when drb3 is written, drb4 and drb5 are also modified with the value written into drb3. when drb4 is written, drb5 is also modified with the value written into drb4. to avoid data corruption in the drb4 and drb5 registers, program drb3 first, followed by drb4 and then drb5. if either drb3 or drb4 are written, this sequence should be followed. bit description 7 reserved. 6:0 row boundary address . . this 7-bit value is compared against the address lines a[28:22] to determine the upper address limit of a particular row (i.e., drb minus previous drb=row size). row boundary address these 8 bit values represent the upper address limits of the 6 rows (i.e., this row minus previous row=row size). unpopulated rows have a value equal to the previous row (row size=0). drb5 reflects the maximum amount of dram in the system. the top of memory is determined by the value written into drb5. if drb5 is greater than 256 mbytes, then 256 mbytes of dram are available. bios must make sure that the drb registers do not reflect more than 256m of main memory. as an example of a general purpose configuration where 3 physical rows are configured for either single-sided or double-sided simms, the memory array would be configured like the one shown in figure 3. in this configuration, the mtxc drives two ras# signals directly to the simm rows. if single-sided simms are populated, the even ras# signal is used and the odd ras# is not connected. if double-sided simms are used, both ras# signals are used.
e 82439TX (mtxc) 39 preliminary simm-0 front simm-0 back simm-1 back simm-3 front simm-3 back simm-2 front simm-2 back ras3# ras2# ras1# ras0# cas7# cas6# cas5# cas4# cas3# cas2# cas1# cas0# drb1 drb2 drb3 simm-1 front drb0 simm-5 front simm-5 back simm-4 front simm-4 back ras5# ras4# drb4 drb5 simm_drb figure 3 . simms and corresponding drb registers the following 2 examples describe how the drb registers are programmed for cases of single-sided and double-sided simms on a motherboard having a total of four 8-byte or eight 4-byte simm sockets. example #1 the memory array is populated with four single-sided 1 mb x 32 simms, a total of 16 mbytes of dram. two simms are required for each populated row making each populated row 8 mbytes in size. drb0=02h populated (2 simms, 8 mbytes this row) drb1=04h populated (2 simms, 8 mbytes this row) drb2=04h empty row drb3=04h empty row drb4=04h empty row drb5=04h empty row example #2 as an another example, the memory array is populated with two 2 mbytes x 32 double-sided simms (one row), and four 4 mbytes x 32 single-sided simms (two rows), yielding a total of 96 mbytes of dram. the drb registers are programmed as follows: drb0=04h populated with 16 mbytes, 1/2 of double-sided simms drb1=08h the other 16 mbytes of the double-sided simm s drb2=10h populated with 32 mbytes, one of the sided simms drb3=18h the other 32 mbytes of single-sided simms drb4=18h empty row drb5=18h empty row
82439TX (mtxc) e 40 preliminary 3.1.23. drth ? ? dram row type register high address offset: 67h default value: s0000000 access: read/write this 8-bit register identifies the type of dram (edo, spm (standard page mode)), or sdram (synchronous dram) used in rows 4 and 5 and should be programmed by bios for optimum performance if edo drams or sdrams are used. the mtxc uses these bits to determine the correct cycle timing to use before a dram cycle is run. bit 7 of this register is used for host frequency detection (hfd). bit 2 of this register is used to determine the muxing results of cke/maa0 and ckeb/maa1. note this register should not be written while dram refresh is enabled. bit description 7 host frequency detection (hfd) . . 1=66 mhz. 0=60 mhz. this bit is initialized to the inverted level on the a27 signal at the rising edge of the rst#. since a27 pin contains an internal weak pulldown, unless an external resistor exits, the field is initialized to 1, indicating 66 mhz. subsequent writes to this field will override the reset strap value. bios can use the value to determine if the system is 60 mhz (external pull-up) or 66 mhz (no strapping). 5:4, 1:0 dram row type (drt). the drt bits select the dram type installed in each physical dram row. each one-of-four bit pairs in this register corresponds to the dram row identified by the corresponding drb register. drt bits dram row 5,1 5 4,0 4 drt dram type value definitions 0,0 spm dram 0,1 edo dram 1,0 sdram 1,1 reserved 6,3 reserved. 2 memory address select enable (maselen). when this bit is set to 1, cke and ckeb are used to propagate the second copy of the ma0 and ma1 lines. cke is muxed with maa0 and ckeb is muxed with maa1. when this bit is set to 0, the cke and ckeb functionality is propagated across these lines. this bit defaults to 0 and bios must set it to 1 to take advantage of the second copy of the ma0 and ma1 lines.
e 82439TX (mtxc) 41 preliminary 3.1.24. drtl ? dram row type register low address offset: 68h default value: 00h access: read/write this 8-bit register identifies the type of dram (edo, spm (standard page mode)), or sdram (synchronous dram) used in rows 0 to 3 and should be programmed by bios for optimum performance if edo dram?s or sdrams are used. the hardware uses these bits to determine the correct cycle timing to use before a dram cycle is run. bit description 7:0 dram row type (drt). the drt bits select the dram type installed in each physical dram row. each one-of-four bit pairs in this register corresponds to the dram row identified by the corresponding drb register. drt bits dram row 7,3 3 6,2 2 5,1 1 4,0 0 drt dram type value definitions 0,0 spm dram 0,1 edo dram 1,0 sdram 1,1 reserved 3.1.25. mtt ? ? multi-transaction timer register (reserved test mode register) address offset: 70h default value: 20h access: read/write mtt is an 8-bit register that controls the amount of time that the mtxc?s arbiter allows a pci initiator to perform multiple transactions on the pci bus. the mtt guarantees the minimum time, measured in pclks, that the pci agent retains the ownership of the pci bus from the initial assertion of grant. bit description 7:2 mtt count value. the number of clocks programmed in the mtt represents the guaranteed time slice (in pclks) allotted to the current agent, after which the mtxc will grant the bus as soon as another pci agent requests the bus. the value of 00h disables this function. the count value should be set to multiples of 4 (i.e., 2 lsbs are ignored). 1:0 reserved. hardwired to 0. (i.e., counter has a resolution of 4 pclks)
82439TX (mtxc) e 42 preliminary 3.1.26. esmramc ? ? extended system management ram control register address offset: 71h default value: 00h access: read/write the extended smram register controls the configuration of extended smram space. mtxc supports two types of smram memory: compatible and extended. the compatible smram (c_smram) memory provides an uncacheable smram memory space below 1 mbytes in the a and b segments. the extended smram (e_smram) memory provides a writeback cacheable smram memory space that is above 1 mbytes. this register provides the following types of control over smram space: where the memory space is located (above 1 mbytes, below 1 mbytes) enabling of smram memory (tseg, 128 kbytes, 256 kbytes, 512 kbytes or 1 mbytes of additional smram memory) for extended smram space only. cacheability control (for the extended smram space only) protection of smram space for non-smm accesses bit description 7 high smram enable (h_smrame) . . 1=enable. 0=disable. this bit enables the high smram memory space to appear in the appropriate physical address locations between 100a0000h and 100f0000h. 6 extended smram error (e_smerr) . . this bit is set when cpu accesses the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit=0. it is software?s responsibility to clear this bit. the software must write a 1 to this bit to clear it. 5 smram cache strategy (sm_cache) . . hardwired to 0. this bit determines how extended smram space is cached (writethru or writeback). since the mtxc supports only writeback for extended smram space, this bit is hardwired to 0. 4 smram_l1_en (sm_l1) . . this bit should be set to 1 if extended smram is being used and the system wishes to l1 writeback cache this memory space. default value for this bit is 0. 3 smram_l2_en (sm_l2). this bit should be set to 1 if extended smram is being used, and there is less than 32 mbytes of dram in the system. setting of this bit when sm_l1 bit=1 allows the extended smram to be writeback cached in the l2. default value for this bit is 0. 2:1 tseg_sz[1-0] (t_sz) . . selects the size of the tseg memory block, if enabled. this memory is taken from the top of dram space, which is no longer claimed by the memory controller (all accesses to this space are sent to the pci bus if tseg_en is set). this memory appears at the physical memory space of 256 mbytes plus the top of memory (tom) minus the size of tseg. this field decodes as follows: bits[1,0] description 00 (tom-128 kb) to tom 01 (tom-256 kb) to tom 10 (tom-512 kb) to tom 11 (tom-1 mb) to tom 0 tseg_en (t_en) . . when g_smrame=1 and t_en=1, the tseg is enabled to appear in the appropriate physical address space.
e 82439TX (mtxc) 43 preliminary 3.1.27. smramc ? ? system management ram control register address offset: 72h default value: 02h access: read/write the smramc register controls how accesses to compatible and extended smram spaces are treated. mtxc supports two types of smram memory: compatible and extended. the open, close, and lock bits function only when g_smrame bit is set to a 1. also, the open bit be reset before the lock bit is set. bit description 7 reserved. 6 smm space open (d_open) . . when d_open=1 and d_lck=0, the smm space dram is made visible even when smiact# is negated. this is intended to help bios initialize smm space. software should ensure that d_open=1 is mutually exclusive with d_cls=1. when d_lck is set to a 1, d_open is reset to 0 and becomes read only. 5 smm space closed (d_cls) . . when d_cls=1, smm space dram is not accessible to data references, even if smiact# is asserted. code references may still access smm space dram. this will allow smm software to reference ? through ? smm space to update the display, even when smm space is mapped over the vga range. software should ensure that d_open=1 is mutually exclusive with d_cls=1. 4 smm space locked (d_lck) . . when d_lck is set to 1, d_open is reset to 0 and both d_lck and d_open become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a power-on reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to ? lock down ? smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 3 global smram enable (g_smrame) . if set to a 1, then compatible smram functions is enabled, providing 128 kb of dram accessible at the a0000h address while in smm (ads# with smiact#). to enable extended smram function this bit has be set to 1. refer to the section on smm for more details. 2:0 compatible smm space base segment (c_base_seg). this field programs the location of smm space. smm dram is not remapped. it is simply ? made visible ? if the conditions are right to access smm space; otherwise, the access is forwarded to pci. c_base_seg=010 selects the smm space as a0000 ? bffffh. all other values are reserved. pci initiators are not allowed to access to smm space. these bits are hardwired to 010.
82439TX (mtxc) e 44 preliminary table 8 summarizes the operation of smram space cycles targeting the smi space addresses. table 8 . smram space cycles g_ s m r a m e d_ l c k d_ c l s d_ o p e n s m i a c t# h_ s m r a m e t s e g_ e n code fetch data access 0 x x x x x x a ? pci s ? pci t ? pci a ? pci s ? pci t ? pci 1 0 0 0 0 0 0 a ? dram s ? pci t ? pci a ? dram s ? pci t ? pci 1 0 0 0 0 0 1 a ? dram s ? pci t ? dram a ? dram s ? pci t ? dram 1 0 0 0 0 1 0 a ? pci s ? dram t ? pci a ? pci s ? dram t ? pci 1 0 0 0 0 1 1 a ? pci s ? dram t ? dram a ? pci s ? dram t ? dram 1 0 x 0 1 x x a ? pci s ? pci t ? pci a ? pci s ? pci t ? pci 1 0 0 1 x 0 0 a ? dram s ? pci t ? pci a ? dram s ? pci t ? pci 1 0 0 1 x 0 1 a ? dram s ? pci t ? dram a ? dram s ? pci t ? dram 1 0 0 1 x 1 0 a ? pci s ? dram t ? pci a ? pci s ? dram t ? pci 1 0 0 1 x 1 1 a ? pci s ? dram t ? dram a ? pci s ? dram t ? dram 1 0 1 0 0 0 0 a ? dram s ? pci t ? pci a ? pci s ? pci t ? pci 1 0 1 0 0 0 1 a ? dram s ? pci t ? dram a ? pci s ? pci t ? pci 1 0 1 0 0 1 0 a ? dram s ? dram t ? pci a ? pci s ? pci t ? pci 1 0 1 0 0 1 1 a ? pci s ? dram t ? dram a ? pci s ? pci t ? pci 1 0 1 1 x x x invalid invalid 1 1 0 0 0 0 0 a ? dram s ? pci t ? pci a ? dram s ? pci t ? pci 1 1 0 0 0 0 1 a ? dram s ? pci t ? dram a ? dram s ? pci t ? dram 1 1 0 0 0 1 0 a ? pci s ? dram t ? pci a ? pci s ? dram t ? pci 1 1 0 0 0 1 1 a ? pci s ? dram t ? dram a ? pci s ? dram t ? dram 1 1 x 0 1 x x a ? pci s ? pci t ? pci a ? pci s ? pci t ? pci 1 1 1 0 0 0 0 a ? dram s ? pci t ? pci a ? pci s ? pci t ? pci 1 1 1 0 0 0 1 a ? dram s ? pci t ? dram a ? pci s ? pci t ? pci 1 1 1 0 0 1 0 a ? pci s ? dram t ? pci a ? pci s ? pci t ? pci 1 1 1 0 0 1 1 a ? pci s ? dram t ? dram a ? pci s ? pci t ? pci notes: 1. a=a segment, s=100a0000h to 100fffffh, and t=t segment. the code fetch and data access columns indicate whether the access is to the pci bus or to main memory dram.
e 82439TX (mtxc) 45 preliminary 3.1.28. mctl ? ? miscellaneous control register address offset: 79h default value: 00h access: read/write bit description 7 reserved. 6 acpi control register enable (acre) . . 0=any cpu access to i/o address 0022h is passed on to the pci bus. 1=any cpu access to i/o address 0022h is processed internally in the mtxc. this bit must be set to 1 before accessing the ? arbiter disable ? bit in the pm2_cntrl register (0022h). 5 suspend refresh type (srt) . . 0=cbr refresh. 1=self refresh. this bit determines what type of dram refresh is used during power on suspend (pos) or suspend to dram modes. this bit applies to edo/fpm dram only. sdram always uses self refresh, regardless of the state of this bit. 4 normal refresh enable (nref_en) . . setting this bit to 1 switches mtxc from suspend refresh to normal refresh. after the reset, this bit must be set by software executing out of eprom. mtxc waits for this bit to be set before exiting out of suspend refresh mode. 3 reserved. 2 internal clock control (gated clock) disable (i cc ) . . 1=disable. 0=enable. this bit, when set to 0, allows the mtxc to reduce its power consumption (via turning off its internal clocks, to specific interfaces) when in chip standby mode. this bit defaults to 0. 1:0 reserved.
82439TX (mtxc) e 46 preliminary 4. 0. functional description 4.1. host interface the host interface of the mtxc is designed to support the pentium microprocessor. the host interface of the mtxc supports 60-, and 66-mhz bus speeds. the intel 430tx pciset supports the pentium microprocessor with a full 64-bit data bus, 32-bit address bus, and associated internal writeback cache logic. host bus addresses are decoded by the mtxc for accesses to main memory, pci memory, and pci i/o. the mtxc also supports the pipelined addressing capability of the pentium microprocessor. 4.2. secondary cache interface the mtxc integrates a high performance writeback second level cache controller using internal/external tags and provides a full first level and second level cache coherency mechanism. the second level cache is direct mapped, nonsectored, and supports a writeback, no write allocate (lines are not allocated on write misses) write policy. the second level cache can be configured to support either a 256-kb or 512-kb cache using synchronous pipelined burst sram or dram cache. one additional pciset signal (krqak) is required to support dram cache. 64-mbytes cacheability coverage is obtained with 8kx8 standard sram to store the tags for 256-kb configuration. for the 512-kb configurations, a 16kx8 standard sram is used to store the tags and the valid bits for 64-mb cacheability. a second level cache line is 32-bytes wide. in the 256-kb configurations, the second level cache contains 8k lines, while the 512-kb configurations contain 16k lines. valid and modified status bits are kept on a per line basis. cacheability of the entire memory space in first level cache is supported, while only the lower 64 mb of main memory is cacheable in the second level cache. table 9 shows the tag sizes needed to support different sizes of cacheability. only main memory controlled by the mtxc dram interface is cached. pci memory is not cached. table 9 . cacheability cache size tag size cacheability 256 kbytes 8k by 8 bits 64 mbytes 512 kbytes 16k by 8 bits (including valid bit) 64 mbytes the following table shows the different standard sram access time requirements for different host clock frequencies. table 10 . sram access time requirements host clock frequency (mhz) pipelined burst clock-to-output access time (ns) tag ram cycle time (ns) 60 10 15 66 8.5 15
e 82439TX (mtxc) 47 preliminary figure 4 and figure 5 show the connections between the mtxc and the external tag ram and data sram. g w e # d [ 7 : 0 ] b w e # d [ 1 5 : 8 ] w e 1 # d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] t i o [ 7 : 0 ] t w e # c c s # c o e # g w e # b w e # d [ 7 : 0 ] w e # o e # a [ 1 2 : 0 ] 8 k x 8 t a g r a m h a [ 1 7 : 5 ] h d [ 6 3 : 5 6 ] h d [ 5 5 : 4 8 ] h d [ 4 7 : 4 0 ] h d [ 3 9 : 3 2 ] h d [ 3 1 : 2 4 ] h d [ 2 3 : 1 6 ] h d [ 1 5 : 8 ] h d [ 7 : 0 ] m t x c 3 2 k x 3 2 s r a m h c l k h a [ 1 7 : 3 ] c a d s # c a d v # a d s # c l k a [ 1 4 : 0 ] c s # g w e # d [ 7 : 0 ] o e # a d s c # b w e # b e [ 3 : 0 ] # d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] h b e [ 7 : 4 ] # b e [ 3 : 0 ] # h b e [ 3 : 0 ] # d [ 1 5 : 8 ] z z z z a d v # a d s p # mtxc_01 figure 4 . mtxc connections for 256k second level cache with pbsram figure 5 shows a 512-kb implementation using four 32kx32 sram. two 64kx32 devices could also be used. in this case, ha18 would not be connected to cs2# (i.e., cs2 and cs2# should be connected to an active state). ha18 should be connected to one of the address lines on the 64kx32 sram and is still required for the tag ram.
82439TX (mtxc) e 48 preliminary g w e # d [ 7 : 0 ] b w e # d [ 1 5 : 8 ] d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] c c s # c o e # g w e # b w e # h d [ 6 3 : 5 6 ] h d [ 5 5 : 4 8 ] h d [ 4 7 : 4 0 ] h d [ 3 9 : 3 2 ] h d [ 3 1 : 2 4 ] h d [ 2 3 : 1 6 ] h d [ 1 5 : 8 ] h d [ 7 : 0 ] 3 2 k x 3 2 s r a m h c l k h a [ 1 7 : 3 ] c a d s # c a d v # a d s # c l k a [ 1 4 : 0 ] c s 1 # g w e # d [ 7 : 0 ] o e # a d s c # b w e # b e [ 3 : 0 ] # d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] t i o [ 7 : 0 ] t w e # d [ 7 : 0 ] w e # o e # a [ 1 3 : 0 ] 1 6 k x 8 t a g r a m h a [ 1 8 : 5 ] m t x c h b e [ 7 : 4 ] # b e [ 3 : 0 ] # h b e [ 3 : 0 ] # d [ 1 5 : 8 ] z z z z g w e # d [ 7 : 0 ] b w e # d [ 1 5 : 8 ] d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] h d [ 6 3 : 5 6 ] h d [ 5 5 : 4 8 ] h d [ 4 7 : 4 0 ] h d [ 3 9 : 3 2 ] h d [ 3 1 : 2 4 ] h d [ 2 3 : 1 6 ] h d [ 1 5 : 8 ] h d [ 7 : 0 ] 3 2 k x 3 2 s r a m h c l k h a [ 1 7 : 3 ] a d s # c l k a [ 1 4 : 0 ] c s 1 # g w e # d [ 7 : 0 ] o e # a d s p # b w e # b e [ 3 : 0 ] # d [ 2 3 : 1 6 ] d [ 3 1 : 2 4 ] h b e [ 7 : 4 ] # b e [ 3 : 0 ] # h b e [ 3 : 0 ] # d [ 1 5 : 8 ] z z z z a d v # a d s p # c s 2 c s 2 # h a 1 8 g n d b w e # g w e # a d s c # a d v # c s 2 c s 2 # c o e # c c s # c a d s # c a d v # v c c h a 1 8 g w e # b w e # mtxc_02 figure 5 . mtxc connections for 512k second level cache with pbsram
e 82439TX (mtxc) 49 preliminary 4.2.1. clock latencies table 11 lists the latencies for various processor transfers to and from the second level cache. table 11 . second level cache latencies with pipelined burst sram cycle type hclk count burst read 3-1-1-1 burst write (write back) 3-1-1-1 single read 3 single write 3 pipelined back-to-back burst reads 3-1-1-1,1-1-1-1 (note 1) notes: 1. the back to ba ck cycles do not account for cpu idle clocks between cycles. 4.2.2. snoop cycles the snoop (or inquire) cycle is used to probe the first level and second level caches when a pci master attempts to access main memory. this is done in order to maintain coherency between the first and second level caches and main memory. to maintain optimum pci bandwidth to dram, the mtxc utilizes a snoop ahead algorithm. once the snoop for the first cache line of a transfer has completed, the mtxc automatically snoops the next sequential cache line. this algorithm enables the mtxc to continue burst transfers across cache line boundaries. reads snoop cycles are performed by driving the pci master address onto the host address bus and asserting eads#. the processor then performs a tag lookup to determine whether the addressed memory is in the first level cache. if the snoop hit is to a modified line in the first level cache (hitm# asserted), then the line in the first level cache is posted to the dram posted write buffers. the line in the second level cache (if it exists) is invalidated. the line in the first level cache is not invalidated if the inv pin on the cpu is tied to the ken# signal from the mtxc. ken#/inv will be driven low by the mtxc with eads# assertion during pci master read cycles. at the same time as the first level snoop cycle, the mtxc performs a tag lookup to determine whether the addressed memory is in the second level cache. a hit to a modified line in the second level cache also results in a writeback to dram posted write buffers if hitm# is not asserted. the pci data is serviced from the dram after the line has been retired to dram. writes pci master write cycles never result in a write directly into the second level cache. a snoop hit to a modified line in either the first or second caches results in a writeback of that line to main memory. if both the first and second level caches have modified lines, then the line is written back from the first level cache. in all cases lines in the first and second level caches are invalidated and the pci write to main memory occurs after the writeback completes. a pci master write snoop hit to an unmodified line in either the first or second level caches results in the line being invalidated. ken#/inv will be driven high by the mtxc with eads# assertion during pci master write cycles.
82439TX (mtxc) e 50 preliminary 4.2.3. dram cache second l evel cache mode dram cache l2 cache implementation is similar to pipelined burst sram, except for the addition of the krqak bi-direct refresh handshake signal between the mtxc and l2 sram. a dram cache type l2 is assumed present when the krqak pin is sampled high during the negation of the reset signal. an internal weak pull-down is used on the mtxc krqak pin to default to a non dram cache l2 mode, if this pin is left unconnected. an external pull-up (10 k w ) must be used on krqak when dram cache sram is used. note that there is no configuration bit associated with the l2 pseudo sram mode. the sram can operate in either master or slave mode via the m/s# strapping bit. in master mode, the sram drives the krqak pin to request a refresh. a slave device never drives krqak, but only monitors it to determine when a refresh period begins. only one sram device within the l2 cache is master enabled. the other sram devices must be slaves. during reset, the master sram and mtxc tri-state their krqak outputs. after the sram reset pin is negated, krqak remains tri-stated for one whole refresh interval and is then driven high by the master sram. the sram signals a refresh request by driving krqak low for 1 clock, high the next clock, and then tri-states on the following clock and waits, sampling the krqak pin. the mtxc after sampling the sram?s request on krqak and after the sram has tri-stated its krqak output, waits for a host bus dead clock and grants an l2 refresh by driving its krqak pin in an identical fashion to the sram?s request signaling. when all sram?s see the refresh grant from the mtxc, they begin their internal refresh cycle for a period of 20 clocks. 4.3. dram interface the mtxc integrates a dram controller that supports a 64-bit memory array from 4 mbytes to 256 mbytes of main memory. the mtxc supports standard page mode (fpm), extended data out (edo) and synchronous dram (sdram) memories using 32-bit wide simm modules, 64-bit wide unbuffered dimm modules and 64-bit wide unbuffered so-dimm modules. dram parity is not supported, and for loading reasons, parity modules should not be used. all three memory types can be mixed and matched. the mtxc generates all dram control signals and multiplexed addresses for the dram array. the address and data flows through the mtxc for all dram accesses. the dram controller interface is fully configurable through a set of control registers. complete descriptions of these registers are given in the mtxc configuration register description. a brief overview of these registers is provided in this section. the mtxc supports page mode drams and edo (extended data out) drams; otherwise known as hyper page mode. the twelve multiplexed address lines, ma[11:0], allow the mtxc to support 4-mbit, 16-mbit, and 64-mbit memory, both symmetrical and asymmetrical addressing. the mtxc has six ras# lines enabling the support of up to six rows of dram. eight cas# lines allow byte control over the array during write operations. the mtxc targets 60 ns (also supports 50 ns and 70 ns) drams, and supports both single- and double-sided dram modules. the mtxc provides cbr refresh and extended cbr refresh in the normal mode and self refresh or cbr (for edos only) during suspend mode. the mtxc also supports sdrams. the fourteen multiplexed address lines, ma[13:0], allow the mtxc to support 16-mbit and 64-mbit sdram devices. the mtxc has six cs# lines (i.e. muxed onto ras#[5:0]). although six cs# signals are provided, due to loading concerns, 5 rows of sdram maximum is recommended. eight dqm lines (i.e., muxed with cas#[7:0]) allow byte control over the array during the write operation. two copies of sras# and scas# signals are provided for encoded sdram commands. the mtxc targets 60- and 66-mhz sdrams and supports both single- and double-sided sdram modules. the dram interface of the mtxc is configured by the dram control mode register (dramc), dram extended control register (dramec), dram timing register (dramt), sdram control register (sdramc), six dram row boundary (drb) registers, and the dram row type (drt) registers. the drb registers define the size of each row in the memory array.
e 82439TX (mtxc) 51 preliminary seven programmable attribute map (pam) registers are used to specify the cacheability, pci enable, and read/write status of the memory space between 640 kbytes and 1 mbytes. each pam register defines a specific address area enabling the system to selectively mark specific memory ranges as cacheable, read only, write only, read/write, or disabled. when a memory range is disabled, all cpu accesses to that range are forwarded to pci. the mtxc also supports one of two memory holes, either from 512 kb ? 640 kb or from 14/15 mb ? 16 mb in main memory. accesses to the memory holes are forwarded to pci. the memory hole can be enabled/disabled through the dram control register. all other memory from 1m to 256 mb is read/write l1 cacheable, and is l2 cacheable up to 64 mb. an optional extended smram dram memory space is also supported in the 256-mb to 512-mb address range. it consists of the 640-kb ? 1-mb dram area aliased at the 256-mb memory segment, and also an optional 128k/256k/512k/1m dram area chopped from the top-of-dram memory and aliased above 256 mb in a similar manner. 4.3.1. dram organization the mtxc integrates a dram controller that supports edo, fpm, and sdram. sdram, edo and fpm dram?s can be mixed between rows, however, a given row must contain only one type of dram. when dram types are mixed (edo, fpm and sdram) each row will run optimized for that particular type of dram. the mtxc supports six rows of memory (six ras#/cs# lines). for maximum memory flexibility and performance, it is recommended that a dram configuration of four rows be used. this allows 64-mbit dram devices to be used as well as the mixing of sdram and edo/fpm. figure 6 shows an edo/fpm configuration using x32 simm modules and figure 7 shows a four row edo/fpm/sdram configuration using x64 dimm modules (or x64 so-dimm). note it is not recommended to mix sdram (which are 3v devices) with 5v edo/fpm simms, unless the sdram and edo/fpm are properly isolated (e.g., isolate the memory data lines with qswitches). mixing 5v and 3v memory is not recommend for reliability reasons. not all sdrams are 5v tolerant.
82439TX (mtxc) e 52 preliminary 3 2 - b i t s i m m 3 2 - b i t s i m m m a [ 1 1 : 0 ] 3 2 - b i t s i m m 3 2 - b i t s i m m w e b # c a s [ 7 : 4 ] # c a s [ 3 : 0 ] # r a s [ 3 : 0 ] # r a s [ 3 : 2 ] # r a s [ 1 : 0 ] # m d [ 6 3 : 0 ] h o s t d a t a b u s m t x c h d [ 6 3 : 0 ] w e a # mtxc_03 figure 6 . fpm/edo four row simm configuration 6 4 - b i t d i m m o r s 0 - d i m m m a [ 1 3 : 0 ] w e b # c a s / d q m [ 7 : 4 ] # c a s / d q m [ 3 : 0 ] # r a s / c s [ 3 : 0 ] # [ 3 : 2 ] # [ 1 : 0 ] # m d [ 6 3 : 0 ] h o s t d a t a b u s m t x c h d [ 6 3 : 0 ] 6 4 - b i t d i m m o r s 0 - d i m m s r a s b # s c a s b # w e a # s r a s a # s c a s a # c k e a c k e b mtxc_04 notes: 1. in a configuration that supports suspend to ram, only cke is used. this is because ckeb is not part of the suspend well the mtxc maintains during a suspend to ram state. 2. in a desktop system that supports edo/fpm, cke and ckeb should be used as the second pair of ma0 and ma1 lines. cke is used as maa0 and ckeb is used as maa1. in this case, they should be evenly distributed throughout the system along with the first pair of ma0 and ma1 lines. figure 7 . fpm/edo/sdram four row dimm or so-dimm configuration
e 82439TX (mtxc) 53 preliminary rules for populating simm modules (or x32 so-dimm modules) simm sockets can be populated in any order (i.e., memory for ras0# does not have to be populated before memory for ras[2:1]# or ras[4:3]# are used). simm socket pairs (i.e., two, 32-bit wide simms ) need to be populated with the same densities. for example, simm sockets for ras0# should be populated with identical densities. however, simm sockets for ras[2:1]# can be populated with different densities than the simm socket pair for ras0#. edos and standard page mode can both be used; however, only one type should be used per simm socket pair. for example, in the table shown below simm sockets for ras[2:1]# can be populated with edos while simm sockets for ras[4:3]# can be populated with standard page mode. if different memory is used for different rows, each row will be optimized for that type of memory. the dram timing register which provides the dram speed grade control for the entire memory array must be programmed to use the timings of the slowest drams installed. rules for populating dimm or so-dimm modules dimm or so-dimm sockets can be populated in any order (i.e., memory for ras0# does not have to be populated before memory for ras[2:1]# or ras[4:3]# are used). 4.3.2. configuration requi rements general configuration requirements in a system that uses 64-mbit sdram, the ras4#/cs4#/ba1 and ras5#/cs5#/ma13 signals are used to provide two additional address lines (ba1 and ma13), and krqak/cs4_64# is used to provide the 5th cs# line, if required. to enable 64-mbit support for four rows of sdram, set sdramc[bit 1] to 1 (offset 54h). to enable 64-mbit support for five rows of sdram, sdramc[bit 1] must be set to 1, and dram cache must not be present in the system (indicated by cec[bit 5]=0, offset 53h). in a five row sdram system that supports 64-mbit sdram devices, the krqak/cs4_64# signal provides the fifth cs# (or cs4_64#) function. this means that a system that supports dram cache, can not support five rows of 64-mbit sdram. however, four rows of 64-mbit sdram with dram cache is supported. in a fpm/edo only configuration, there are no restrictions on using 64-mbit devices (i.e., all six rows can support 64-mbit dram devices. however, sdramc[bit 1] must be set to 1 if more than four rows of edo/fpm are used. this allows the ras4# and ras5# functions to be used. driven on ras5#/cs5#/ ma13 driven on ras4#/cs4#/ ma13 driven on krqak/ cs4_64# 64-mbit (sdram) 64-mbit (edo/fpm) bit 1, reg 54h=0 ras5#/cs5# ras4#/cs4# krqak no yes (6 rows) bit 1, reg 54h=1 and dram cache is present* ma13 ba1 (bank select) krqak yes (4 rows) yes (4 rows) bit 1, reg 54h=1 and dram cache is not present 1 ma13 ba1 (bank select) ras4#/ cs4_64# yes (5 rows) yes (5 rows) notes: 1. the presence of dram cache is indicated by the value in bit 5, register 53h. due to loading, using sdram x4 devices is not recommended. buffering of sdram rows is not supported in a five row system, the 5th row is intended to be implemented with dram devices that are soldered down on the motherboard. if a dimm or a simm is used in the 5th row, it should not be used as an upgrade path
82439TX (mtxc) e 54 preliminary by the end user; the size and type of dram that can be implemented in the 5th row is limited (see the bullets below). the total memory supported is 256 mb, even though it is possible to populate the six rows with more than 256 mb. this limit must be ensured by the system bios. edo/fpm only configuration requirements if more than four rows of x4 dram devices + one row of x8 dram devices of memory is supported, it is recommended that all six rows be buffered. ma and mwe# enable signals should be buffered. in a system that only supports x8 or x16 devices (i.e., x4 devices not supported), six rows of memory can be supported without buffering. maximum load supported without buffers: four rows of x4 dr am devices + one row of x8 dram devices. a second pair or ma0 and ma1 signals are provided by muxing cke with maa0 and ckeb with maa1. in a desktop system, it is required that the second pair of ma lines be used to support 5-2-2-2 edo performance in more than two rows of memory. the second pair of ma lines are not required in a mobile system, assuming x4 devices are not used. the ma functionality is selected via dramc[bit 2] (67h). sdram only configuration requirements maximum rows supported; five rows of x8 devices. sdram/edo/fpm mixing configuration requirements if sdram and edo/fpm are mixed in a system, the configuration is limited to a maximum of four rows (two rows of x4 edo/fpm and two rows of x8 or x16 sdram). if only x8 or x16 edo/fpm and sdram devices are used (i.e., not x4?s), five rows can be supported. sdrams can be mixed with edo/fpm on a row by row basis (e .g., row 0 can be populated with sdrams while row 3 is populated with edo/fpm). a second pair or ma0 and ma1 signals are provided by muxing cke with maa0 and ckeb with maa1. in a desktop system, it is required that the second pair of ma lines be used to support 5-2-2-2 edo performance in more than two rows of memory. the second pair of ma lines are not required in a mobile system, assuming x4 devices are not used. the ma functionality is selected via dramc[bit 2] (67h). table 12 provides a summary of the characteristics of memory configurations supported by the mtxc. minimum values listed are obtained with single-sided simms or dimms. maximum values are obtained with double-sided simms or dimms. note that, for a 64-bit wide memory array, a minimum of two 32-bit wide dram simms are required in any specific row. the minimum values used are also the smallest upgradeable memory size. please note that edo/fpm can also come on x64 dimm modules.
e 82439TX (mtxc) 55 preliminary table 12 . minimum (upgradeable) and maximum memory size for each configuration (dram) dram dram dram dram simm dram address size dram size tech. density width ss x32 ds x32 addressing row col min. (up) (1 row) max. (6 rows) 4m 512k 8 512k 1m asymmetric 10 9 4 mb 24 mb 1m 4 1m 2m symmetric 10 10 8 mb 48 mb 16m 1m 16 1m 2m symmetric 10 10 8 mb 48 mb 1m 16 1m 2m asymmetric 12 8 8 mb 48 mb 2m 8 2m 4m asymmetric 11 10 16 mb 96 mb 4m 4 4m 8m symmetric 11 11 32 mb 192 mb 4m 4 4m 8m asymmetric 12 10 32 mb 192 mb 64m 2m 32 2m 4m asymmetric 12 9 16 mb 96 mb 4m 16 4m 8m symmetric 11 11 32 mb 192 mb 4m 16 4m 8m asymmetric 12 10 32 mb 192 mb 8m 8 8m 16m asymmetric 12 11 64 mb 256 mb 16m 4 16m 32m symmetric 12 12 128 mb 256 mb table 13 . minimum (upgradeable) and maximum memory size for each configuration (sdram) sdram sdram sdram sdram dimm sdram address size sdram size tech. density width ss x64 ds x64 addressing row column min. (up) (1 row) max. (6 rows) 16m 1m 16 1m 2m asymmetric 12 8 8 mb 48 mb 2m 8 2m 4m asymmetric 12 9 16 mb 96 mb 4m 4 1 4m 8m asymmetric 12 10 32 mb 192 mb 64m 2m 32 2m 4m asymmetric 12 9 16 mb 96 mb 2m 32 2m 4m asymmetric 13 8 16 mb 96 mb 4m 16 4m 8m asymmetric 14 8 32 mb 192 mb 8m 8 8m 16m asymmetric 14 9 64 mb 256 mb 16m 4 1 16m 32m asymmetric 14 10 128 mb 256 mb notes: 1. functionally the 430tx supports x4 sdram devices. however, due t o loading reasons, it is not recommended that x4 devices be used in 60-mhz and 66-mhz designs.
82439TX (mtxc) e 56 preliminary the memory organization shown below represents the maximum 256 mb of address space. accesses to memory space above top-of-dram (< 256 mb), video buffer, or the memory gaps (if enabled) are forwarded to pci, and these regions are not cacheable. below 1 mb, there are several memory segments which have selectable cacheability. none of the dram space occupied by the video buffer (except for smm usage) or the memory space gaps is remapped (and is therefore ? lost ? ). 4 g b d o s a p p l i c a t i o n s ( n o r e a d / w r i t e p r o t e c t ) ( a l w a y s c a c h e a b l e ) n o n - c a c h e a b l e i n l 2 , c a c h e a b l e i n l 1 f o r w a r d e d t o p c i ( n o n - c a c h e a b l e ) 2 5 6 m b + 6 4 0 k b o p t i o n a l h i s m r a m s h a d o w a r e a 3 8 4 k b ( c a c h e a b l e ) f o r w a r d e d t o p c i ( n o n - c a c h e a b l e ) o p t i o n a l t s e g ( c a c h e a b l e ) 1 2 8 k b / 2 5 6 k b / 5 1 2 k b / 1 m b 2 5 6 m b + t o p - o f - d r a m f o r w a r d e d t o p c i ( n o n - c a c h e a b l e ) c a c h e a b l e o p t i o n a l m e m o r y s p a c e g a p 2 5 6 m b 6 4 m b 1 6 m b 1 4 / 1 5 m b 1 m b 7 6 8 k b 6 4 0 k b 5 1 2 k b 0 c a c h e a b l e e x p a n s i o n a n d b i o s r e g i o n ( c a c h e a b l e s e g m e n t s ) v i d e o b u f f e r ( s m m s p a c e n o n - c a c h e a b l e ) o p t i o n a l m e m o r y s p a c e g a p a l i a s e d t s e g s y s t e m d r a m t o p - o f - d r a m ( d r b 5 ) t o p - o f - m a i n m e m o r y a l i a s e d mtxc_08 figure 8 . memory space organization
e 82439TX (mtxc) 57 preliminary 4.3.3. dram address transl ation the multiplexed row/column address to the dram memory array is provided by the ma[11:0] signals (ma[13:0] for sdram 64-mbit support). the ma bits are derived from the host or pci address bus as defined by the table 14 . the mtxc supports a 2k byte page size only. the ma lines are translated from the address lines a[26:3] for all memory accesses. table 14 . mtxc dram address map summary addr ma13 ma12/ ba1 ma11/ ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 row a24 a23 a11 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 col a23 a26/ a11 a11/ a25 ? v ? a11/ a24/ a26 a11/ a22/ a23/ a25 a10 a9 a8 a7 a6 a5 a4 a3 notes: 1. v=valid level (either 0 or 1) used for sdrams. it is 1 during the initialization sequence. it is 0 during normal mode of operation. 2. ba0 and ba1 are the muxed bank selects for sdram. bank select ba1 is required for 64-mbit sdram support. 4.3.4. dram paging if dramc[bit 4]=1, the mtxc keeps the page open until a page or row miss occurs. if dramc[bit 4]=0 (default), the dram page is kept open when: cpu host bus is non-idle, or pci interface owns the bus. 4.3.5. dram types 4.3.5.1. fpm mode the mtxc, as a default, supports the standard fast page mode (fpm) dram. 4.3.5.2. edo mode extended data out (or hyper page mode) dram is designed to improve the dram read performance. edo dram holds the memory data valid until the next cas# falling edge. compared to standard page mode dram which tri-states the memory data when cas# negates to precharge. with edo, the cas# precharge overlaps the memory data valid time. this allows cas# to negate earlier while still satisfying the memory data valid window time. 4.3.5.3. sdram mode synchronous dram (sdram) implements a fully synchronous interface as compared to a conventional dram whose timing delays are related to the rising and falling edges of the ras#, cas#, and we# input signals. the 430tx supports all of the features and timings as shown in the ? sdram pc ? specification. the objective of the sdram pc specification is to enable low cost and easily manufactureable sdrams for the main stream volume
82439TX (mtxc) e 58 preliminary desktop and mobile pc?s. there are three grade parts defined for the 430tx. all of the speed grade conform to the sdram pc specification . for information on the performance of each of the speed grade parts, refer to the dram performance section. the three speed grade parts are shown in table 15 . table 15 . sdram speed grade parts speed grade cas latency (cl) ras to cas (trcd) system frequency 66.67 mhz 3 3 60/66 mhz 66.67 mhz 3 2 60/66 mhz 66.67 mhz 2 2 60/66 mhz sdram command reference the 430tx supports the following commands: command command mode register set (mrs) no operation (nop) activate bank (act) auto refresh cbr (refr) read bank (rd) data write/output enable write bank (wr) data mask/output disable precharge all banks (pall) self refresh entry deselect device self refresh exit table 16 mrs command (mode register set) supported by the mtxc. table 16 . command fields a11 a10 a9 a8 a7 a[6:4] a3 a[2:0] 0 0 0 0 0 cl wt bl cas latency field (cl) wrap type field (wt) burst length field (bl) bits[6:4] cas latency bit 3 type bits[2:0] burst length 010 2 0 x 010 4 011 3 1 interleave all other x all other x the linear order addressing is not supported. notes: 1. x=don?t care. these modes are don?t care for mtxc specific implementation.
e 82439TX (mtxc) 59 preliminary 4.3.6. auto detection the sdram, fpm, and edo detection is performed by bios. note that when accessing any of the dram related registers (i.e., 54h ? 68h), refresh should be turned off via the dram control register (dramc). 4.3.7. dram performance the dram performance is controlled by the dram timing register, processor pipelining, and by the type of dram used (edo or fpm or sdram). table 17 depicts both edo and standard page mode optimum timings. for read cycles, clocks counts are measured from ads# to brdy#. for write cycles, the measurement is broken up into two parts. the first part consists of the rate of posting data in to the cpu to dram posted write buffers. this is measured from ads# to brdy#. the second part consists of the retire rate from posted write buffers to the dram. the leadoff for retiring is measured from the clock after brdy# assertion to the cas# assertion. table 17 lists the performance summary for 60 ns edo/fpm drams. the four row column is assuming each row is populated with a maximum of 16, x4 devices=64 dram devices. the five row column is assuming each of the first four rows is populated with a maximum of 16, x4 devices and the fifth row is populated with a maximum of eight, x8 devices=72 dram devices. the six row column assumes that each of the six rows can be populated with a maximum of 16, x4 devices. the felo and sld bits are used to control the leadoff for read cycles (page hit, row miss, and page miss). each bit removes one clock from the leadoff, when enabled. note that felo impacts edo only and must be disabled for fpm. the dlt bits are used to control the base starting point for the leadoff for read/write cycles (page miss and row miss, only).
82439TX (mtxc) e 60 preliminary table 17 . edo/ standard page mode performance summary (60 ns drams) processor cycle type (pipelined) 60/66 mhz w/ four rows 60/66 mhz w/ five rows 60/66 mhz w/ six rows buffered dram type burst read page hit 5-2-2-2 6-3-3-3 6-3-3-3 edo read row miss 1 8-2-2-2 9-3-3-3 10-3-3-3 edo read page miss 11-2-2-2 12-3-3-3 13-3-3-3 edo back-to-back burst reads page hit 5-2-2-2-3-2-2-2 6-3-3-3-4-3-3-3 6-3-3-3-4-3-3-3 edo burst read page hit 6-3-3-3 7-4-4-4 7-4-4-4 fpm burst read row miss 1 9-3-3-3 9-4-4-4 9-4-4-4 fpm burst read page miss 12-3-3-3 12-4-4-4 12-4-4-4 fpm back-to-back burst read page hit 6-3-3-3-3-3-3-3 7-4-4-4-4-4-4-4 7-4-4-4-4-4-4-4 fpm write page hit 2,3,4 3 3 3 edo/fpm write row miss 2,3,4 6 6 7 edo/fpm write page miss 2,3,4 9 9 10 edo/fpm posted write 3,4 3-1-1-1 3-1-1-1 3-1-1-1 edo/fpm write retire rate from posted write buffer -2-2-2 -3-3-3 -3-3-3 edo/fpm single writes 2 2 3 edo/fpm reg 56h, bit 4 (sld) 5 0 0 0 edo/fpm reg 56h, bit 5 (felo) 6 1 1 1 edo reg 56h, bit 5 (felo) 6 0 0 0 fpm reg 58h, bits[6:5] (drbt) 2 1 1 edo/fpm reg 58h, bits[4:3] (dwbt) 2 1 1 edo/fpm reg 58h, bits[1:0] (dlt) 1 1 0 edo/fpm reg 56h, bit 6 (rra) 0 0 0 edo/fpm notes: 1. the row miss cycles assume that the new page is closed from the prior cycle. due to the ma[13:0] to ras# setup requirements, if the page is open, 2 clocks are added to the leadoff. 2. this cycle timing assumes the write buffer(dwb) is empty. 3. write timing is measured from the clock after brdy# is returned to the cpu up to cas# assertion for that cycle. 4. write data is always posted as 3-1-1-1 (ads# to brdy#), if write buffers is available. 5. this bit (sld) should be set to a 1 (speculative leadoff disable) in systems with cache and to 0 in systems without cache. 6. when set to 1, enables fast timing for edo timing only. enables one hclk pull in for page hit, page miss, and row miss cycles.
e 82439TX (mtxc) 61 preliminary table 18 lists the performance summary for sdram. the cl= 3 column represents a cas latency of 3 part with a ras to cas (trcd) of two clocks. the cl=2 column represents a cas latency of two part. the performance numbers in table 18 assume each row is populated with a maximum of eight, x8 devices=40 sdram devices. the sld bit (page hit, row miss, and page miss) is used to control the leadoff for read cycles. this bit removes one clock from the leadoff, when enabled. table 18 . sdram performance summary processor cycle type 60/66 mhz cl=3 five rows (max) 60/66 mhz cl=2 five rows (max) burst read page hit 7-1-1-1 6-1-1-1 read row miss 1 9-1-1-16 8-1-1-1 read page miss 12-1-1-16 11-1-1-1 back-to-back burst reads page hit 7-1-1-1 2-1-1-1 6-1-1-1 2-1-1-1 write page hit 2,3 3 3 write row miss 2,3 6 5 write page miss 2,3 9 8 posted write 2,3 3-1-1-1 3-1-1-1 write retire rate from posted write buffer -1-1-1 -1-1-1 reg 54h, bit 5 (rco) 5 1 0 reg 54h, bit 4 (cl) 0 1 reg 54h, bit 3 (rt) 0 1 reg 56h, bit 4 (sld) 4 0 0 notes: 1. the row miss cycle assumes that the new page is closed from the prior cycle. 2. this cycle timing assumes the write buffer(dwb) is empty. 3. write data is always posted as 3-1-1-1 (ads# to brdy#), if write buffers is available. 4. this bit (sld) must be set to a 1 (speculative leadoff disable) in systems with cache and to 0 in systems without cache. 5. for a cl=3 part that can not meet a ras to cas timing (trcd) of two hclks , rco can be set to 0. this will add an hclk to the leadoff cycle for row miss and page miss cycles.
82439TX (mtxc) e 62 preliminary 4.3.8. dram refresh mtxc supports cas-before-ras# (cbr) refresh and self refresh. the refresh rate is controlled via the dram refresh rate field in the dram control register (dramc). when a refresh request is generated, it is placed in a four entry queue. the dram controller services a refresh request when the refresh queue in not empty and the controller has no other requests pending. when the refresh queue is full, refresh becomes the highest priority request and will be serviced next by the controller. refresh is only performed on rows that are populated (i.e., ? smart refresh ? ). the controller determines which rows are populated by looking at the drb registers. note that refresh has to be disabled before the refresh rate is changed. refer to bit 5 in the mctl register (offset 79h) for suspend refresh information. 4.4. pci clk control (clkrun#) 4.4.1. clocking states there are three main states in the clocking protocol: clock running: the clock is running and the bus is operational. about to stop: the central resource has indicated on the clkrun# line that the clock is about to stop. clock stopped: the clock is stopped with clkrun# being monitored for a restart 4.4.2. operation the mtxc is a clkrun# master device and behaves according to the rules for a master device. the piix4 companion chip controls the clocks in the system and is the clkrun# central resource. please refer to the latest ? pci mobile design guide ? for more information. 4.5. smram memory space the mtxc supports the use of main memory as system management ram (smram), enabling the use of system management mode. the mtxc supports two smram options; compatible smram (c_smram) and extended smram (e_smram). 4.5.1. compatible smram (c _smram) this is the traditional smram feature supported in intel pcisets. when this function is enabled via c_base_seg[2:0]=010 and g_smrame=1 of the smramc register, the mtxc reserves 000a0000h through 000bffffh (a and b segments) of the main memory for use as noncacheable smram. cpu accesses to segments a and b while not in smm (i.e., smiact# is negated) are always forwarded to the pci bus. cpu accesses to segments a and b while in smm (i.e., smiact# is asserted) are forwarded to either dram or pci bus, depending on the value of bits[6:0] of the smramc register. pci masters cannot access the smram area of the main memory. when a pci master tries to access the smram space, the mtxc does not respond to the pci cycle (i.e., devsel# is not asserted). 4.5.2. extended smram (e_s mram) this feature in the mtxc extends the smram space up to 1 mbytes and provide writeback cacheability. this feature requires that smi handlers execute above 1 mbytes which will require rewriting the existing code to
e 82439TX (mtxc) 63 preliminary operate properly above 1 mbytes. however once this is done, then smi handlers execute at full processor performance. an error status bit is set in the extended smram control register if the cpu tries to access the extended smram space while smiact# is negated and d_open bit is 0. this access is forwarded to pci bus and may result in a master abort condition. extended smram feature allows up to 1 mbyte of smram space to be writeback cacheable. this memory space consists of any dram not used by the system (as shadow space etc.) between 640 kbytes and 1 mbyte (this memory space is referred to as high memory in this document), and an optional block of memory referred to as the ? tseg ? . the tseg is either a 128 kbyte, 256 kbyte, 512 kbytes, or 1 mbytes block of memory, as defined by tseg_sz[1:0] of the smramc register. when tseg is enabled, the tseg block of memory is disabled from the top of memory and the system bios should report a main memory size of (memorize - tseg) to the os. the two areas of memory available for smram when extended smram is enabled are: physical address dram address 100a0000h to 100fffffh 000a0000h to 000fffffh (high mem) 10000000h plus tom minus tseg_sz to 10000000h plus tom tom minus tseg_sz to tom (tseg) extended smram option has the following dram memory available to it: table 19 . extended smram dram memory regions dram area size/availability a segment 64 kbytes always available if enabled (i.e., h_smram=1 and g_smrame=1) b segment 64 kbytes always available if enabled (i.e., h_smram=1 and g_smrame=1) c segment 64 kbytes available if not used for shadowing (as defined by pam register) and enabled (i.e., h_smram=1 and g_smrame=1) d segment 64 kbytes available if not used for shadowing (as defined by pam register) and enabled (i.e., h_smram=1 and g_smrame=1) e segment 64 kbytes available if not used for shadowing (as defined by pam register) and enabled (i.e., h_smram=1 and g_smrame=1) f segment 64 kbytes only available for suspend/resume (as defined by pam register) if enabled (i.e., h_smram=1 and g_smrame=1) tseg 128k, 256k, 512k or 1m bytes available if enabled (i.e., tseg_en=1 and g_smrame=1)
82439TX (mtxc) e 64 preliminary as with the compatible smram solution, mtxc does not claim any bus master access to the extended smram memory ranges defined above. the cpu can access these memory ranges by one of the following mechanisms: the processor generating an access to one of the defined memory ranges while in the smm (smiact# is active). a processor access to any of the defined ranges while not in smm (smiact# is inactive) and with the d_opn bit reset will be forwarded to pci bus and a status bit is set in the smramc register. the processor generating an access to one of the defined memory ranges while the d_opn bit is set. any modified write access of the processor is allowed to write into the smram space, regardless of the state of the d_opn, d_cls, or smiact# signals. the cacheability of smram space is dependent on how much physical dram is available in the system. if the system has less than 32 mbytes of dram, the smram is cached in both the l1 and l2. if the system has more than 32 mbytes of dram, the smram is cached in only the l1. 4.5.3. smram programming c onsiderations when using the extended smram configuration, the smi handler software must be extremely careful when accessing dram memory in the 100a0000h to 100fffffh memory range. first, if this area of memory is accessed while the cpu is not in smm mode and the d_opn bit is not set, the mtxc will forward the cycle to pci bus which may cause a fatal system error and system shutdown. second, only areas within the 100a0000h to 100fffffh region that have been selected as smram space should be accessed; otherwise, the l1 and l2 caches will become incoherent, which will cause a future system error. any memory in normal dram space that is not used in os or application space can be used as smram memory. 4.6. low power states mtxc supports five types of low power states: chip standby, power on suspend (pos), suspend to ram (str), suspend to disk (std), and dynamic stop clock. the table 20 summarizes the various mtxc?s low power states. table 20 . 430tx low power state summary pm mode description exit latency target chip standby when mtxc?s cpu and pci busses are both idle, mtxc enters this state. no delay dynamic stop clock mtxc provides provisions that enable transitioning the cpu in and out of the stop clock state in an active system. this includes the ability to disable the system arbiter and transition the memory controller in and out of the suspend refresh state. <10 ms powered on suspend (pos) system plls are powered down, only running clock is the rtc clock and the susclk. mtxc maintains dram refresh using susclk. <10 ms suspend to ram (str) cpu complex (cpu and l2) and pci interface are powered off. only the rtc clock and susclk are running. mtxc maintains dram refresh using susclk. ~1 sec suspend to disk(std) cpu complex (cpu and l2), dram and pci interface are powered off. ~30 sec
e 82439TX (mtxc) 65 preliminary the 430tx system maintains a very low power cpu complex by utilizing the different power down features available from the cpu, cache data rams and utilizing leading edge low power design techniques in the 430tx system components. the 430tx components work in unison to dynamically control the cpu complexes power state without adversely affecting performance. the following gives a brief description of how the 430tx system components achieve these low power states. the mtxc and piix4 work in unison to maintain a very low power l2 subsystem without adversely affecting peak performance. note there are some system restrictions when dram cache is implemented in a system that supports stp_clk, pos, and str power management modes. since krqak is not implemented in the ? suspend well, ? the correct operation of krq ak is not guaranteed when the system enters the above mentioned power management modes. to avoid data corruption in the l2 cache, a system that implements the stp_clk, pos, and str modes must abide by the following rules: 1. before entering these power management modes, the dram cache must be flushed so that all modified lines end up in system memory. 2. after exiting these power management modes, the dram cache must be reinitialized. 4.6.1. chip standby the mtxc also supports a chip standby mode. when the mtxc determines that both its cpu interface and pci interface are idle, it will dynamically place itself into a very low power state. while in chip standby state the mtxc is able to respond to new cpu or pci bus master accesses with no performance penalty. this provides very optimized power/performance characteristics because the cpu interface are idle for large periods of time. the mtxc enters chip standby mode when the following conditions are true: host bus idle pci bus idle normal mode (i.e., not test mode) not in reset state internal operations idle entering the chip standby state is not dependent on any timer expiration. when the above conditions are met, the mtxc can enter the chip standby state as soon as it can. 4.6.2. suspend/resume the mtxc supports pos, str, std and soff (soft off) suspend states. the mtxc supports the pos mode by maintaining all of its power planes when in the suspend state. the mtxc supports the str modes by isolating its cpu and pci interfaces, and only maintaining the dram refresh off the susclk signal. when exiting the str modes, the mtxc?s core well is reset and its context is lost (the power management context is not lost however). the mtxc supports the std and soff modes by being totally powered off.
82439TX (mtxc) e 66 preliminary mtxc rsm well dram refresh suspend rasx#, casx#, wex# cke susclk, susstat1# core well cpu/l2 interface pci interface mtxc_05 figure 9 . mtxc power planes 4.6.2.1. power transition changes the mtxc supports several suspend modes that support the piix4 system suspend states. table 21 illustrates what suspend mode the mtxc enters upon the appropriate piix4 suspend mode. table 21 . power transition states piix4 suspend state mtxc suspend state mtxc description pos pons all interfaces enabled, clocks stopped. str poffs cpu, l2, pci interfaces disabled std off chip is off. off/soft off off chip is off. the core logic should be reset when the pci bus is reset. this means that the refresh logic and power sequencing logic is not reset during resumes (part of the resume well).
e 82439TX (mtxc) 67 preliminary 4.7. pci interface the mtxc integrates a high performance interface to the pci local bus taking full advantage of the high bandwidth and low latency of pci. the mtxc is fully pci 2.1 compliant. table 22 lists the pci bus commands supported. five pci masters are supported by the integrated arbiter including the piix4 and four general pci masters. the mtxc acts as a pci master for cpu accesses to pci. the pci bus is clocked at one half the frequency of the cpu clock. this divided synchronous interface minimizes latency for cpu-to-pci cycles and pci-to-main memory cycles. the mtxc integrates posted write buffers for cpu memory writes to pci. back-to-back sequential memory writes to pci are converted to burst writes on pci. this feature allows the cpu to continue posting dword writes at the maximum bandwidth for the pentium processor for the highest possible transfer rates to the graphics frame buffer. read prefetch and write posting buffers in the mtxc enable pci masters to access main memory at up to 120 mb/sec. the mtxc incorporates a snoop ahead feature that allows pci masters to continue bursting on both reads and writes even as the bursts cross cache line boundaries. the mtxc forwards each of the cpu shutdown, halt, and stop grant cycles to the pci bus as special cycles. these cycles are terminated on pci as master abort and a brdy# is returned to the cpu. the stop grant cycle is propagated with 0002h in the message field and 0012h in the message dependent data field. table 22 . pci commands c/be# command target support initiator support 0000 interrupt acknowledge no yes 0001 special cycle no yes 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved no no 0101 reserved no no 0110 memory read yes yes 0111 memory write yes yes 1000 reserved no no 1001 reserved no no 1010 configuration read no yes 1011 configuration write no yes 1100 memory read multiple as memory read no 1101 dual address cycle no no 1110 memory read line as memory read no 1111 memory write and invalidate as memory write no
82439TX (mtxc) e 68 preliminary 4.8. system arbitration the mtxc?s pci bus arbiter allows pci peer-to-peer traffic concurrent with cpu main memory/second level cache cycles. the arbiter supports five pci masters. req[3:0]#/gnt[3:0]# are used by pci masters other than the pci-to-isa expansion bridge (piix4). phld#/phlda# are the arbitration request/grant signals for the piix4 and provide guaranteed access time capability for isa masters. phld#/phlda# also optimize system performance based on the piix4 known policies. a r b i t e r p h l d # r e q 0 # r e q 1 # r e q 2 # r e q 3 # p h l d a # g n t 0 # g n t 1 # g n t 2 # g n t 3 # mtxc_06 figure 10 . pci arbiter 4.8.1. priority scheme and bus grant the highest priority requester is determined by a fixed order queue together with a highest priority pointer. although the priority ring is fixed, the highest priority pointer moves to determine which pci agent is at the top (and bottom) of the queue. the arbiter counts three grant assertions to requesters different than the one it is currently granting (and all grants within mtt are collapsed to one) to decide when it?s time to let the host in. the grant signals (gntx#) are normally negated after recognition of frame# assertion, or 16 pclks from grant assertion, if no cycle has started.
e 82439TX (mtxc) 69 preliminary cpu/pci priority queue pci priority queue cpu pci pci pci phld# req0# req1# phld# req2# req3# mtxc_07 notes: 1. in the pci priority queue, the last agent granted is always dropped to the bottom of the queue for the next arbitration cycle, but the order of the chain is always preserved. 2. in the pci priority queue, if phld is at the bottom of the queue, the upper phld slot is masked. this prevents back-to- back phld grants, if other pci request are pending. 3. in the cpu/pci priority queue, the cpu is granted high priority status after 3 consecutive pci grants. if three consecutive pci grants have not been counted down, then the cpu can be granted the bus as the low priority agent. figure 11 . arbitration priority rotation
82439TX (mtxc) e 70 preliminary multi-transaction timer (mtt) the priority chain algorithm has been enhanced by the multi-transaction timer (mtt) mechanism. once a pci agent is granted, the mtt is started. this timer then counts down in pci clocks from its preset value to zero. until the timer expires, that agent will be promoted to being the highest priority pci agent for the next grant event. 4.8.2. cpu policies the cpu never explicitly requests the bus. instead, the arbiter grants the bus to the cpu when: the cpu is the highest priority pci agents do not require main memory (peer-to-peer transfers or bus idle) and the pci bus is not currently locked by a pci master when the cpu is granted as highest priority, the mlt timer is used to guarantee a minimum amount of system resources to the cpu before another requesting pci agent is granted. 5. 0. clocks and reset 5.1. clock generation and distribution the mtxc and cpu should be clocked from one clock driver output to minimize skew between the cpu & mtxc. 5.2. reset sequencing the mtxc is asynchronously reset when the rst# signal is asserted. the mtxc arbiter includes support for pci central resource functions. these functions include driving the ad[31:0],c/be[3:0]#, and the par signals when no one is granted the pci bus and the pci bus is idle. the mtxc drives 0?s on these signals during these times, plus during reset.
e 82439TX (mtxc) 71 preliminary 6. 0. pinout information m n p r t u v w y v c c - s u s r a s 3 # / c s 3 # h d 2 3 h d 2 6 h d 2 5 h d 2 8 b o f f # v c c v c c - s u s c a s 6 # / d q m 6 # r a s 1 # / c s 1 # s c a s - a # s r a s - b # h d 7 h d 2 1 h d 1 9 h d 2 4 e a d s # v c c ( c p u ) v c c ( c p u ) v c c v c c - s u s r a s 2 # / c s 2 # m w e # s u s s t a t 1 # m d 1 1 b e 7 # h d 3 3 h d 3 2 h d 3 5 b r d y # v s s v s s v s s v s s r a s 5 # / c s 5 # / m a 1 3 m d 5 3 s c a s - b # m d 2 0 m d 2 2 h d 1 2 h d 1 7 h d 2 2 h d 2 0 a d s # v s s d / c # h i t m # w / r # s m i - a c t # a 6 t i o 3 v c c m a 3 r s t # v s s c a s 3 # / d q m 3 # c a s 7 # / d q m 7 # c a s 4 # / d q m 4 # s u s - c l k h d 8 h d 1 8 h d 1 4 h d 1 6 a 2 0 a 1 6 a 1 2 a 5 a 2 3 a 2 2 a 2 9 c a d s # t i o 6 t i o 0 m a 4 m a 1 0 m a 9 c a s 0 # / d q m 0 # c a s 5 # / d q m 5 # c k e / m a a 0 h d 6 h d 1 5 h d 1 0 h d 1 3 a 1 9 a 1 4 a 9 a 8 a 2 1 a 2 6 a 3 c o e # g w e # t i o 2 m a 0 m a 1 k r q a k / c s 4 _ 6 4 # m w e - b # r a s 4 # / c s 4 # / b a 1 c a s 2 # / d q m 2 # h d 4 h d 5 h d 9 h d 1 1 a 1 8 a 1 5 a 1 1 a 3 1 a 2 5 a 2 4 a 3 0 c a d v # c c s # t i o 7 t i o 4 c k e b / m a a 1 t e s t # m a 6 m a 8 c a s 1 # / d q m 1 # h d 0 h d 2 h d 1 h d 3 a 1 7 a 1 3 a 1 0 a 7 a 2 7 a 2 8 a 4 b w e # t w e # t i o 1 t i o 5 m a 5 m a 2 m a 7 m a 1 1 / b a 0 r a s 0 # / c s 0 # k l c a c h e # m d 1 m d 2 h d 3 4 b e 0 # b e 1 # b e 2 # k e n # v s s v s s v s s v s s h c l - k i n m d 3 4 m d 3 9 m d 7 m d 5 4 b e 3 # b e 4 # b e 5 # b e 6 # a h o l d v s s v s s v s s v s s v c c m d 3 m d 3 7 m d 3 8 m d 6 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 a b c d e f g h j h d 3 9 h d 4 0 h d 4 6 h d 4 4 m / i o # m d 1 6 m d 0 m d 4 m d 5 m d 1 7 h d 3 7 h d 3 6 h d 4 2 h d 3 8 v s s v s s v s s v s s m d 5 2 m d 5 5 m d 2 3 h d 6 2 a d 3 0 a d 2 8 a d 2 6 a d 2 3 a d 2 0 a d 1 7 c / b e 1 # a d 1 3 a d 1 0 c / b e 0 # a d 5 a d 2 m d 3 1 m d 1 4 m d 1 3 m d 6 1 m d 1 2 m d 5 9 m d 5 8 h d 5 9 h d 6 0 h d 6 1 a d 2 5 a d 2 2 a d 1 9 a d 1 6 a d 1 5 a d 1 2 a d 9 a d 7 a d 4 c l k - r u n # m d 4 7 m d 6 3 m d 4 5 m d 2 8 m d 6 2 m d 1 0 m d 4 2 h d 5 5 h d 5 8 h d 5 7 p h l d # p h l d - a # a d 2 4 r e q 0 # g n t 0 # r e q 1 # g n t 1 # r e q 2 # g n t 2 # r e q 3 # g n t 3 # m d 4 6 m d 3 0 m d 4 4 m d 2 6 m d 5 7 m d 0 9 h d 5 2 h d 5 4 h d 5 6 h d 5 3 l o c k # f r a - m e # i r d y # t r d y # d e v - s e l # p c l k - i n s t o p # v c c m d 1 5 v c c 5 - r e f v s s m d 4 9 m d 2 5 m d 4 1 m d 2 4 m d 5 6 h d 6 3 a d 3 1 a d 2 9 c / b e 3 # a d 2 1 a d 1 8 c / b e 2 # a d 1 4 a d 1 1 a d 8 a d 6 a d 3 a d 1 a d 0 p a r m d 2 9 m d 6 0 m d 2 7 m d 4 3 h d 4 8 h d 4 7 h d 5 1 h d 5 0 v c c v c c ( c p u ) v c c v c c m d 4 8 m d 3 3 m d 8 m d 4 0 m d 1 9 h d 4 5 h d 4 1 h d 4 9 h d 4 3 h l o - c k # v c c ( c p u ) m d 3 5 m d 3 2 m d 1 8 m d 3 6 m d 5 0 h d 2 7 h d 3 0 h d 2 9 h d 3 1 n a # a d 2 7 s r a s - a # m d 2 1 m d 5 1 mtxc_pin figure 12 . mtxc pinout (top view)
82439TX (mtxc) e 72 preliminary table 23 . mtxc alphabetical pin list pin ball a10 y07 a11 w07 a12 u07 a13 y06 a14 v06 a15 w06 a16 u06 a17 y05 a18 w05 a19 v05 a20 u05 a21 v09 a22 u10 a23 u09 a24 w10 a25 w09 a26 v10 a27 y09 a28 y10 a29 u11 a3 v11 a30 w11 a31 w08 a4 y11 a5 u08 a6 t11 a7 y08 a8 v08 a9 v07 table 23 . mtxc alphabetical pin list pin ball ad0 a15 ad1 a14 ad10 b10 ad11 a10 ad12 c09 ad13 b09 ad14 a09 ad15 c08 ad16 c07 ad17 b07 ad18 a07 ad19 c06 ad2 b13 ad20 b06 ad21 a06 ad22 c05 ad23 b05 ad24 d06 ad25 c04 ad26 b04 ad27 a04 ad28 b03 ad29 a03 ad3 a13 ad30 b02 ad31 a02 ad4 c12 ad5 b12 ad6 a12 table 23 . mtxc alphabetical pin list pin ball ad7 c11 ad8 a11 ad9 c10 ads# t05 ahold l05 be0# k02 be1# k03 be2# k04 be3# l01 be4# l02 be5# l03 be6# l04 be7# m01 boff# p05 brdy# m05 bwe# y12 c/be0# b11 c/be1# b08 c/be2# a08 c/be3# a05 cache# j05 cads# u12 cadv# w12 cas0#/dqm0# u18 cas1#/dqm1# w20 cas2#/dqm2# v20 cas3#/dqm3# t17 cas4#/dqm4# t19 cas5#/dqm5# u19
e 82439TX (mtxc) 73 preliminary table 23 . mtxc alphabetical pin list pin ball cas6#/dqm6# p17 cas7#/dqm7# t18 ccs# w13 cke/maa0 u20 ckeb/maa1 w16 clkrun# c13 coe# v12 d/c# t07 devsel# e09 eads# r05 frame# e06 gnt0# d08 gnt1# d10 gnt2# d12 gnt3# d14 gwe# v13 hclkin k16 hd0 y01 hd1 y03 hd10 v03 hd11 w04 hd12 t01 hd13 v04 hd14 u03 hd15 v02 hd16 u04 hd17 t02 hd18 u02 hd19 r03 table 23 . mtxc alphabetical pin list pin ball hd2 y02 hd20 t04 hd21 r02 hd22 t03 hd23 p01 hd24 r04 hd25 p03 hd26 p02 hd27 n01 hd28 p04 hd29 n03 hd3 y04 hd30 n02 hd31 n04 hd32 m03 hd33 m02 hd34 k01 hd35 m04 hd36 j02 hd37 j01 hd38 j04 hd39 h01 hd4 w01 hd40 h02 hd41 g02 hd42 j03 hd43 g04 hd44 h04 hd45 g01 table 23 . mtxc alphabetical pin list pin ball hd46 h03 hd47 f02 hd48 f01 hd49 g03 hd5 w02 hd50 f04 hd51 f03 hd52 e01 hd53 e04 hd54 e02 hd55 d01 hd56 e03 hd57 d03 hd58 d02 hd59 c01 hd6 v01 hd60 c02 hd61 c03 hd62 b01 hd63 a01 hd7 r01 hd8 u01 hd9 w03 hitm# t08 hlock# g05 irdy# e07 ken# k05 krqak/ cs4_64# v17 lock# e05
82439TX (mtxc) e 74 preliminary table 23 . mtxc alphabetical pin list pin ball m/io# h05 ma0 v15 ma1 v16 ma10 u16 ma11/ba0 y19 ma2 y17 ma3 t14 ma4 u15 ma5 y16 ma6 w18 ma7 y18 ma8 w19 ma9 u17 md0 h17 md1 j16 md10 c19 md11 r20 md12 b18 md13 b16 md14 b15 md15 e13 md16 h16 md17 h20 md18 g18 md19 f20 md2 j17 md20 m19 md21 n19 md22 m20 table 23 . mtxc alphabetical pin list pin ball md23 j20 md24 e19 md25 e17 md26 d18 md27 a19 md28 c17 md29 a17 md3 l17 md30 d16 md31 b14 md32 g17 md33 f17 md34 k17 md35 g16 md36 g19 md37 l18 md38 l19 md39 k18 md4 h18 md40 f19 md41 e18 md42 c20 md43 a20 md44 d17 md45 c16 md46 d15 md47 c14 md48 f16 md49 e16 table 23 . mtxc alphabetical pin list pin ball md5 h19 md50 g20 md51 n20 md52 j18 md53 m17 md54 k20 md55 j19 md56 e20 md57 d19 md58 b20 md59 b19 md6 l20 md60 a18 md61 b17 md62 c18 md63 c15 md7 k19 md8 f18 md9 d20 mwe# r18 mweb# v18 na# n05 par a16 pclkin e10 phld# d04 phlda# d05 ras0#/cs0# y20 ras1#/cs1# p18 ras2#/cs2/# r17
e 82439TX (mtxc) 75 preliminary table 23 . mtxc alphabetical pin list pin ball ras3#/cs3# n17 ras4#/cs4#/ ba1 v19 ras5#/cs5#/ ma13 m16 req0# d07 req1# d09 req2# d11 req3# d13 rst# t15 scasa# p19 scasb# m18 smiact# t10 srasa# n18 srasb# p20 stop# e11 susclk t20 susstat1# r19 table 23 . mtxc alphabetical pin list pin ball test# w17 tio0 u14 tio1 y14 tio2 v14 tio3 t12 tio4 w15 tio5 y15 tio6 u13 tio7 w14 trdy# e08 twe# y13 w/r# t09 v cc f05, l16, r15, f15, e12, p15, f14, t13 table 23 . mtxc alphabetical pin list pin ball v cc (cpu) f06, g06, r07, r06 v cc (sus) r16, n16, p16 v cc 5ref e14 v ss e15, j9, j10 j11, j12, k09, k10, k11, k12, l09, l10, l11, l12, m09, m10, m11, m12, t06, t16
82439TX (mtxc) e 76 preliminary 7. 0. mtxc package information this specification outlines the mechanical dimensions for the mtxc. the package is a 324 pin ball grid array (bga). t o p v i e w p i n # 1 c o r n e r d 1 d e e 1 f p i n # 1 i . d . s i d e v i e w a 1 a 2 a c mtxc_10 figure 13 . mtxc 324-pin ball grid array (bga)
e 82439TX (mtxc) 77 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y e pin #1 corner 324 balls 20 x 20 matrix b j i e top view mtxc_09 figure 14 . mtxc 324-pin ball grid array (bga) ball pattern
82439TX (mtxc) e 78 preliminary table 24 . mtxc 324-pin ball grid array (bga) symbol e=1.27 (solder ball pitch) min 1 nominal 1 max 1 a 1.95 2.13 2.28 a1 0.50 0.60 0.70 a2 1.12 1.17 1.22 d 26.80 27.00 27.20 d1 24.00 24.70 e 26.80 27.00 27.20 e1 24.00 24.70 i 1.44 ref. j 1.44 ref. m 2 20 (depopulated) n 3 324 b 0.60 0.76 0.90 c 0.32 0.36 0.40 f 8.05 ref. remark 2 layer notes: 1. all dimensions are in millimeters. 2. ?m? represents the maximum solder b all matrix size. 3. ?n? represents the maximum allowable number of solder balls.
e 82439TX (mtxc) 79 preliminary 8. 0. testability 8.1. nand tree mode a nand tree mode is provided for automated test equipment (ate) board level testing. the nand tree allows the tester to set the connectivity of each of the mtxc?s signal pins. in mobile/desktop mode, the nand tree mode is activated by driving the test pin test# low when reqx# pins are at 0010. if test# is negated at any time, the test mode is deactivated and the mtxc goes back to normal operation. there is no guarantee that upon re-entering normal operation the chip will function properly, if the test mode was entered while the mtxc was not in a completely idle state. the mtxc has several test modes to improve board manufacturing. if the test# signal is asserted (driven low), the value on the req[3:0]# indicates the test mode to enable. the test mode enabled at the falling edge of test# will remain enabled until test# is negated. table 25 shows each test mode and the value of req#[3:0] required to enable it. all other values of req[3:0]# while test# is active, are reserved and should not be asserted by the customer. table 25 . test modes req[3:0]# test# phld# test mode description 0010 0 x nand chain float outputs, enable nand chains on gnt[3:0]# 1110 0 1 id/rev code drives device id on ad[31:16] and revision id on ad[7:0] 1110 0 0 mid code drives manufacture id on ad[31:0] 1111 0 x disable test mode 1 disables any active test mode, puts mtxc back into normal mode notes: 1. it is recommended to assert rst# if this mode is used, to guarantee pins and pciset will function normally. 8.2. nand chain mode in nand tree mode, all outputs are tri-stated, except for gnt#[3:0]. these pins contain the nand chain. note, also, that the internal pull-ups and pull-downs are still active. because of the 282 pins in the nand chain, it must be separated into 4 chains. two chains contain 72 pins each, 1 chain contains 70 pins, and 1 chain contains 68 pins. the mtxc remains in this mode until a new test mode is selected or rst# is asserted. the hclk and pclk are part of the nand chain and must be deactivated during this test.
82439TX (mtxc) e 80 preliminary hclk and pclk need to run for a few clocks in the beginning to put the mtxc in the nand chain mode. during the testing of chains 2 and 3, susstat# will be held high throughout the test. rst#, test#, and susstat1# are not part of the nand chain. the following tables show the pin order for each chain: table 26 . chain #0 (gnt#0) pin name chain element a25 ch0_00 a7 ch0_01 a10 ch0_02 a21 ch0_03 a23 ch0_04 smiact# ch0_05 a31 ch0_06 a18 ch0_07 hd3 ch0_08 a12 ch0_09 a14 ch0_10 hd11 ch0_11 a19 ch0_12 a16 ch0_13 hitm# ch0_14 hd13 ch0_15 d/c# ch0_16 hd0 ch0_17 hd10 ch0_18 hd16 ch0_19 hd6 ch0_20 hd14 ch0_21 boff# ch0_22 hd18 ch0_23 table 26 . chain #0 (gnt#0) pin name chain element hd24 ch0_24 hd8 ch0_25 hd19 ch0_26 hd7 ch0_27 hd31 ch0_28 hd26 ch0_29 hd27 ch0_30 hd33 ch0_31 ahold ch0_32 be5# ch0_33 be6# ch0_34 hd34 ch0_35 be2# ch0_36 be0# ch0_37 hd37 ch0_38 be1# ch0_39 hd36 ch0_40 hd41 ch0_41 hd52 ch0_42 cache# ch0_43 hd47 ch0_44 hd44 ch0_45 hd49 ch0_46 hd54 ch0_47 table 26 . chain #0 (gnt#0) pin name chain element hd55 ch0_48 hd57 ch0_49 hlock# ch0_50 hd53 ch0_51 hd60 ch0_52 hd62 ch0_53 hd61 ch0_54 ad30 ch0_55 ad25 ch0_56 ad22 ch0_57 ad24 ch0_58 ad27 ch0_59 ad19 ch0_60 c/be3# ch0_61 req0# ch0_62 ad20 ch0_63 ad21 ch0_64 trdy# ch0_65 ad16 ch0_66 c/be2# ch0_67 c/be1# ch0_68 ad14 ch0_69 ad12 ch0_70 ad13 ch0_71
e 82439TX (mtxc) 81 preliminary table 27 . chain #1 (gnt#1) pin name chain element a24 ch1_00 a27 ch1_01 a26 ch1_02 a13 ch1_03 a8 ch1_04 w/r# ch1_05 a11 ch1_06 a17 ch1_07 a15 ch1_08 a5 ch1_09 a9 ch1_10 hd1 ch1_11 hd9 ch1_12 a20 ch1_13 hd2 ch1_14 hd5 ch1_15 hd4 ch1_16 ads# ch1_17 hd15 ch1_18 eads# ch1_19 hd20 ch1_20 hd17 ch1_21 hd22 ch1_22 hd12 ch1_23 table 27 . chain #1 (gnt#1) pin name chain element hd28 ch1_24 hd21 ch1_25 na# ch1_26 hd25 ch1_27 brdy# ch1_28 hd23 ch1_29 hd35 ch1_30 hd29 ch1_31 hd30 ch1_32 be7# ch1_33 hd32 ch1_34 be3# ch1_35 be4# ch1_36 hd39 ch1_37 hd45 ch1_38 hd42 ch1_39 hd38 ch1_40 hd40 ch1_41 hd48 ch1_42 ken# ch1_43 hd46 ch1_44 hd43 ch1_45 hd51 ch1_46 hd58 ch1_47 table 27 . chain #1 (gnt#1) pin name chain element hd56 ch1_48 hd50 ch1_49 m/io# ch1_50 hd59 ch1_51 hd63 ch1_52 phld# ch1_53 ad31 ch1_54 lock# ch1_55 ad28 ch1_56 frame# ch1_57 ad29 ch1_58 phlda# ch1_59 irdy# ch1_60 ad26 ch1_61 ad23 ch1_62 ad17 ch1_63 devsel# ch1_64 ad18 ch1_65 req1# ch1_66 ad15 ch1_67 pclkin ch1_68 ad11 ch1_69 ad10 ch1_70 ad9 ch1_71
82439TX (mtxc) e 82 preliminary table 28 . chain #2 (gnt#2) pin name chain element a28 ch2_00 a29 ch2_01 a3 ch2_02 a30 ch2_03 a4 ch2_04 coe# ch2_05 bwe# ch2_06 ccs# ch2_07 ma5 ch2_08 ma10 ch2_09 krqak/ cs4_64# ch2_10 ma7 ch2_11 ma11 ch2_12 ma6 ch2_13 ma9 ch2_14 mweb# ch2_15 ras0# ch2_16 ras4# ch2_17 ras2# ch2_18 cas7# ch2_19 cas5# ch2_20 cas6# ch2_21 cke/maa0 ch2_22 table 28 . chain #2 (gnt#2) pin name chain element cas4# ch2_23 susclk ch2_24 srasa ch2_25 md11 ch2_26 md53 ch2_27 scasb# ch2_28 md22 ch2_29 md6 ch2_30 md34 ch2_31 md39 ch2_32 md7 ch2_33 md54 ch2_34 hclkin ch2_35 md55 ch2_36 md5 ch2_37 md17 ch2_38 md2 ch2_39 md50 ch2_40 md1 ch2_41 md0 ch2_42 md18 ch2_43 md16 ch2_44 md19 ch2_45 md40 ch2_46 table 28 . chain #2 (gnt#2) pin name chain element md32 ch2_47 md25 ch2_48 md26 ch2_49 md42 ch2_50 md48 ch2_51 md49 ch2_52 md59 ch2_53 md43 ch2_54 md30 ch2_55 md27 ch2_56 md28 ch2_57 md12 ch2_58 md60 ch2_59 clkrun# ch2_60 ad0 ch2_61 ad2 ch2_62 stop# ch2_63 ad4 ch2_64 ad3 ch2_65 ad5 ch2_66 ad7 ch2_67 ad6 ch2_68 req2# ch2_69
e 82439TX (mtxc) 83 preliminary table 29 . chain #3 (gnt#3) pin name chain element a22 ch3_00 cadv# ch3_01 a6 ch3_02 twe# ch3_03 gwe# ch3_04 cads# ch3_05 tio1 ch3_06 tio3 ch3_07 tio7 ch3_08 tio6 ch3_09 tio2 ch3_10 tio5 ch3_11 tio4 ch3_12 tio0 ch3_13 ma0 ch3_14 ma2 ch3_15 ma4 ch3_16 ckeb/ maa1 ch3_17 ma1 ch3_18 ma3 ch3_19 ma8 ch3_20 cas1# ch3_21 cas3# ch3_22 table 29 . chain #3 (gnt#3) pin name chain element cas0# ch3_23 cas2# ch3_24 mweb# ch3_25 ras1# ch3_26 ras3# ch3_27 ras5# ch3_28 scasa ch3_29 md21 ch3_30 srasb# ch3_31 md51 ch3_32 md20 ch3_33 md37 ch3_34 md38 ch3_35 md3 ch3_36 md52 ch3_37 md23 ch3_38 md4 ch3_39 md36 ch3_40 md56 ch3_41 md8 ch3_42 md9 ch3_43 md33 ch3_44 md24 ch3_45 table 29 . chain #3 (gnt#3) pin name chain element md41 ch3_46 md57 ch3_47 md35 ch3_48 md58 ch3_49 md10 ch3_50 md44 ch3_51 md62 ch3_52 md15 ch3_53 md46 ch3_54 md45 ch3_55 md61 ch3_56 md63 ch3_57 md29 ch3_58 md13 ch3_59 md47 ch3_60 req3# ch3_61 md14 ch3_62 par ch3_63 md31 ch3_64 ad1 ch3_65 c/be0# ch3_66 ad8 ch3_67

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